Microsoft Technology Licensing, LLC

Other

Michael G Love

John Allen Tardif

Louis F Coffin, Iii

Jack A Scheuer

Kenneth D Ray

Ling Tony Chen

Felix Stefan Domke

Harjit Singh

Garrett Douglas Blankenburg

Walker Chamberlain Robb

Paul Paternoster

Avdhesh Chhodavdia

Gregory George Williams

Stephen Z Au

Philip Forman

A hardware debug system includes a target chip comprising one or more target chip registers and one or more target chip ports, wherein at least one of the one or more target chip ports is used as a target chip debug port, and a debug host with one or more debug host ports, wherein at least one of the one or more debug host ports is connected to the target chip debug port via a hardware debug bus, wherein the debug host is configured to load at least one target chip setting into the one or more target chip registers that enables the target chip to boot via the hardware debug port using the hardware debug bus.

Hardware debug host

A system-on-chip (SoC) includes multiple hardware modules that are implemented on a substrate. The hardware modules include a plurality of hardware and software security features and the SoC provides one or more external interfaces for accessing the security features. A validation module, implemented in the boot code of the SoC for example, manages security certificates to control access to the plurality of security features. Each security certificate includes one or more unique identifiers corresponding to one or more hardware modules in the SoC and access control settings for one or more security features of the one or more hardware modules. The security certificate additionally includes a certificate signature signed by a secure key.

Security certificates for system-on-chip security

The water jug attachment is an essentially rectangular support device wherein the rectangular device is supported by three legs, wherein the single rear leg is mounted in the center of the back of the rectangular device and operates as a jack in order to lift and support the rear of the jug and tilt it toward the spout or spigot as the volume in the jug declines due to use allowing the water in the jug to pour out of the spigot.

Water jug attachment

A system-on-chip (SoC) is provided that includes a centralized access enablement circuit for controlling access to a plurality of security features for multiple hardware modules of the system. Progressive security states corresponding to different stages in a chip's design, manufacture and delivery are utilized to enable different access control settings for security features as a part moves from design to end-use. The access enablement circuit for a SoC implementing different security states provides individual access control settings for security features in the different security states. One-time programmable memory and register controls are provided in one embodiment that allow different access control settings for an individual security feature in the same or different security states of the system.

Access enablement security circuit

This disclosure involves an on-chip bus architecture involving an on-chip bus that includes a collector node and at least one device node. Each device node is in communication with an on-chip device. The collector node is capable of conducting multiple outstanding transactions with a plurality of on-chip devices over the on-chip bus wherein each on-chip device transmits all of its data signals across the on-chip bus in the form of packets. The on-chip bus includes at least one bus register, and each of the multiple on-chip devices includes at least one device register. The on-chip bus can provide top level register to register communications between the device register and the bus register. In one version, the on-chip bus is a distributed packet on-chip (DPO) bus.

On-chip bus

Various embodiments provide means by which a video signal, associated with a multi-region visual display intended for presentation on a single display screen, can be processed in a manner that enables separate regions to be ascertained, and then split off onto different display screens. Detection algorithms can process the video signal in a manner that detects the divisions between the different regions that are intended for display on a single display screen. Once the divisions are detected, the video signal is processed to split the separate regions onto different display screens.

Video division detection methods and systems

In an implementation of a display source divider, a video generation system generates a video display source that includes display data for multiple display regions on a display device. For example, a gaming system generates a video display source that includes display data partitioned display, where each region of the partitioned display corresponds to a different player of the gaming system. A display source divider receives the video display source and generates multiple video streams each corresponding to a different display region of the partitioned display.

Display source divider

Video division detection

In an implementation of a display source divider, a video generation system generates a video display source that includes display data for multiple display regions on a display device. For example, a gaming system generates a video display source that includes display data for a partitioned display, where each region of the partitioned display corresponds to a different player of the gaming system. A display source divider receives the video display source and generates multiple video streams each corresponding to a different display region of the partitioned display.

In an implementation of a display source divider, a video generation system generates a video display source that includes display data for multiple display regions which include left eye display regions and right eye display regions of head display devices. For example, a gaming system generates a video display source that includes display data for left eye display regions and right eye display regions of head display devices that each correspond to a different player of the gaming system. A display source divider receives the video display source and generates a left eye display video stream and an associated right eye display video stream for each of the head display devices.

A memory controller is utilized to overcome NAND flash memory's propensity for comprising bad blocks of memory. The memory controller utilizes minimal hardware and is essentially transparent to a device requesting access to the NAND memory. A NAND flash memory device is configured to comprise a set of main blocks of memory and a set of auxiliary blocks of memory. Each block is divided into pages of memory and each page includes metadata. The metadata includes a block status indicator, indicating whether a block is good or bad. When receiving a request to access a page in the NAND flash memory, if the block in which the page resides is good, that block is accessed. If the block is bad, auxiliary memory is searched until a block containing the address of the bad block in its metadata is found. The found block is accessed in lieu of the bad block.

NAND flash memory management

This disclosure involves an on-chip bus architecture involving an on-chip bus that includes a collector node and at least one device node. Each device node is in communication with an on-chip device. The collector node is capable of conducting the multiple outstanding transactions with a plurality of on-chip devices over the on-chip bus wherein each on-chip device transmits all of its data signals across the on-chip bus in the form of packets. The on-chip bus includes at least one bus register, and each of the multiple on-chip devices includes at least one device register. The on-chip bus can provide top level register to register communications between the device register and the bus register. In one version, the on-chip bus is a distributed packet on-chip (DPO) bus.

A composite socket member for use with a prosthetic appliance for a residual limb which comprises an outer socket which defines an inner cavity generally conforming to the outer surface of a residual limb, an inner socket which defines an inner cavity and being adapted to receive said residual limb, with said inner socket conforming to the shape of said outer socket and when nested within the cavity of said outer socket defines an air space between the inner surface of said outer socket and the outer surface of said inner socket and an inflatable bladder being disposed between the inner surface of said outer socket and the outer surface of said inner socket. The inner socket contains at least one flex area in its side wall at a preselected weight-bearing location whereby upon inflation of said bladder, pressure is applied by said bladder against said side wall at said preselected weight-bearing location of the residual limb to control the movement and rotation stability of said prosthetic appliance. A method for making the composite socket member is also disclosed.

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San Francisco, CA, United States of America

Michael G Love