Fujitsu Corporation

Cisco Technology, Inc.

Uv Networks, Inc.

Michael G Lee

Solomon I Beilin

Wen-chou Vincent Wang

William T Chou

Michael G Peters

James J Roman

Kishio Yokouchi

Alexei L Glebov

David Kudzuma

Larry Louis Moresco

Yasuhito Takahashi

Thomas Joel Massingill

Som S Swamy

Tetsuzo Yoshimura

Dashun Steve Zhou

Teruo Murase

Masaaki Inao

Albert Wong Chan

Yashuhito Takahashi

Mark Thomas McCormack

Kuo-Chuan Liu

Chihiro Uchibori

Hunt Hang Jiang

David A Horine

Connie M Wong

Lidu Huang

Edward A Krause

Shigenori Aoki

Takuji Yamamoto

Peter Albert Monta

David Dung Ngo

Charbel Yamuni

Theresa M Larson

A method of updating a neural network may be provided. A method may include selecting a number of neurons for a layer for a neural network such that the number of neurons in the layer is less than at least one of a number of neurons in a first layer of the neural network and a number of neurons in a second, adjacent layer of the neural network. The method may further include and at least one of inserting the layer between the first layer and the second layer of the neural network and replacing one of the first layer and the second layer with the layer to reduce a number of connections in the neural network.

Neural network connection reduction

A computer-implemented method for representation of weight values in an artificial neural network using inter-group indexing may include, in an artificial neural network that includes neurons and synaptic connections between the neurons with each of the synaptic connections including a weight, arranging the weights in ascending order. The method may also include dividing the arranged weights into groups based on approximately linear patterns of the weights. The method may further include designating a base group and the other groups as dependent groups. The method may also include storing in memory values of the weights in the base group. The method may further include storing in the memory a group index for each of the dependent groups. The method may also include storing in the memory an index for each of the weights in the dependent groups corresponding to one of the weights in the base group without storing in the memory values of the weights in the dependent groups.

Representation of weight values in an artificial neural network using inter-group indexing

An interposer for an electronic circuit chip package may include a substrate, a recess, first conductive vias, and second conductive vias. The substrate may have a first surface, a second surface substantially parallel to and opposite the first surface, a third surface substantially parallel to the first surface and the second surface, and an orthogonal surface that is substantially orthogonal to and intersects the first surface and the third surface. The recess may be formed in the substrate and defined by the third surface and the orthogonal surface. The first conductive vias may pass from the second surface to the first surface. The second conductive vias may pass from the second surface to the third surface.

Interposer for integrated circuit chip package

A semiconductor assembly includes a first substrate and a chip. The chip is coupled to and spaced apart from the substrate. Further, the chip has a first surface facing the substrate. The chip also has a warpage profile indicating stress imparted on the chip following a reflow operation. The assembly includes a back layer disposed on the chip on a second surface substantially opposite from the first surface. The back layer has a non-uniform thickness. Additionally, the thickness of the back layer on each of a plurality of elements of the chip is based on the warpage profile.

Method and system for controlling chip warpage during bonding

An agent manages multipath communications between a first network and a second network. The first network and a second network are wirelessly coupled by links through a plurality of wireless cellular devices. A link status monitor maintains a list of wireless cellular devices with bridging capability available for multipath communications between the first and second networks. A packet scheduler identifies segments of received packets originating from the second network and assigns one or more wireless cellular devices selected from the list to the identified segments. A packet transmitter encapsulates the segments of packets so identified and addresses the encapsulated segments to the assigned wireless cellular devices.

High capacity network communication link using multiple cellular devices

A method for alignment of a first substrate coupled to a second substrate includes determining an inclination angle for the first substrate or the second substrate due to warpage. The method includes determining a joint height difference based on the inclination angle and configuring a size for one or more bond pads based on the joint height difference.

Method and system for controlling chip inclination during flip-chip mounting

In one embodiment, an interconnect structure between an integrated circuit (IC) chip and a substrate comprises a plurality of materials.

Hybrid interconnect technology

A semiconductor assembly is provided that includes a substrate. A first set of non-conductive hedges is disposed on and protrudes from a first surface of the substrate. A chip is coupled to and spaced apart from the substrate. The chip has a second surface facing the first surface of the substrate. A second set of non-conductive hedges is disposed on and protrudes from the second surface of the chip. The first set of hedges is configured and positioned to engage the second set of hedges to restrict movement of the substrate with respect to the chip. The second set of hedges is configured and positioned to engage the first set of hedges to restrict movement of the chip with respect to the substrate.

Method and system for providing a reliable semiconductor assembly

A semiconductor assembly is provided that includes a substrate that has a first surface. A chip is coupled to the substrate. The chip has a second surface that faces the first surface of the substrate. The chip is spaced apart from the substrate forming a gap. At least a portion of the substrate is coupled to the chip by solder bumps. The solder bumps include a deformable material, such that as a height of the gap between the chip and the substrate increases, the solder bumps deform into a stretched state. An underfill material is applied between the substrate and the chip. The underfill material substantially fills the gap between the chip and the substrate and surrounds the solder bumps in the stretched state. Barricades comprising non-conductive protrusions are disposed between the first surface of the substrate and the second surface of the chip. The barricades confine the solder bumps in a compressed state.

Method and system for providing a low-profile semiconductor assembly

An optical assembly is provided that includes a substrate. The substrate has one or more optical waveguides. A component is coupled to and spaced apart from the substrate. The component has one or more photodetectors. One or more flexible optical pillars is disposed between the optical waveguides and the photodetectors. The flexible optical pillars are aligned by one or more alignment structures. The flexible optical pillars are optically transmissive and configured to transmit light from the optical waveguides to the photodetectors.

Alignment structures for an optical assembly

A semiconductor assembly is provided that includes a first substrate that has a first surface. A second substrate is coupled to and spaced apart from the first substrate. The second substrate has a second surface facing the first surface of the first substrate. The second substrate includes a set of cavities. A set of non-conductive pillars is disposed on and protrudes from the first surface of the first substrate. The set of non-conductive pillars is configured and positioned to engage the set of cavities of the second substrate to align the second substrate with the first substrate.

Method and system for providing an aligned semiconductor assembly

An optical beam splitter includes an input waveguide, two or more branching arms, two or more fan-out arms, and two or more output waveguides. The input waveguide receives an input light beam. The two or more branching arms are coupled to the input waveguide at a separation point and split the input light beam at the separation point into two or more light beams. Each fan-out arm is coupled to one of the branching arms and fans-out one of the two or more light beams to a predetermined output pitch. Each output waveguide is coupled to one of the fan-out arms and transmits one of the two or more light beams out of the optical beam splitter.

Optical beam splitter

Disclosed are optical modulators that provide high-speed modulation capability and compact size. In exemplary modulator embodiments, the branch waveguide cores are formed in different processing layers than the input waveguide core, and light is coupled from an input waveguide core to two branch waveguide cores along diagonal directions. The construction enables the input waveguide core to be made of low-loss material compared to the electro-optic material of the branch waveguide cores. Also disclosed are interconnect apparatuses that can be used in processing systems. Exemplary interconnect apparatuses provide various configurations of components that enable high-speed modulation and compact size. The exemplary interconnect apparatuses may use the exemplary optical modulators disclosed herein.

Optical interconnect apparatuses and electro-optic modulators for processing systems

The present invention generally relates to circuits on the nanotechnology scale. Specifically, it is directed to methods of fabricating carbon nanotube-based (i.e., CNT-based) circuits. The method involves providing a mixture of carbon nanotubes that is substantially disaggregated and patterning carbon nanotubes through the use of electrostatic forces. Carbon nanotubes in the mixture are typically disaggregated through the introduction of positive charge on the individual nanotubes. The patterning of the carbon nanotubes is typically accomplished using electrostatic attraction between pre-formed metal lines and the charged carbon nanotubes.

High density interconnections with nanowiring

The present invention is directed to an apparatus and related methods related to an optical bump for optically coupling devices. An exemplary apparatus includes a first device, a second device, and at least one optical bump. The first device has a first surface including at least one first optically active area. The second device has a second surface including at least one second optically active area positioned in an opposed and spaced-apart relationship with respect to the at least one first optically active area. The first surface is separated from the second surface by a distance. The at least one optical bump is coupled to the first surface between the at least one first optically active area and the at least one second optically active area. The at least one optical bump has a height that is less than the distance between the first surface and the second surface. The at least one optical bump is configured to couple light between the at least one second optically active area and the at least one first optically active area.

Growing community of inventors

San Jose, CA, United States of America

Michael G Lee