Sun Microsystems, Inc.

Silicon Image Gmbh

Other

Gula Consulting Limited Liability Company

Lattice Semiconductor Corporation

Alandro Consulting Ny LLC

Michael G Lavelle

Michael Frank Deering

David C Kehlet

Ewa M Kubalska

Nandini Ramani

Brian D Emberling

Michael Wasserman

Yan Yan Tang

Mark E Pascual

Nathaniel David Naegle

Patrick Shehane

Ranjit S Oberoi

Elena M Ing

Alex N Koltzoff

Stephen A Schlapp

Wing-Cheong Tang

James Gregory Hanko

J Duane Northcutt

Anthony S Ramirez

Glenn Gracon

Philip C Leung

Brian Keith Schmidt

Scott R Nelson

Paul Daniel Wolf

Justin Michael Mahan

Kevin Tang

Carol A Lavelle

Huang Pan

Curtis R Priem

Satyanarayana Nishtala

William L Lynch

James D Lyle

Daniel Chao

Daniel E Lenoski

Thomas P Webber

Daniel S Rice

Assana Fard

Deron D Johnson

Thomas W Bowman

Peter A Mehring

Roger Swanson

Wayne A Morse

Wayne Eric Burk

Guy Moffat

N David Naegle

Michael W Schimpf

Steven Te-Chun Yu

David Naegle

Yi-Ming Tian

Rangit S Oberoi

Douglas C Twilleager

Christopher R Owen

A high-speed ring topology. In one embodiment, two base chip types are required: a 'drawing' chip, LoopDraw, and an 'interface' chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).

Scalable high performance 3D graphics

In some embodiments, an apparatus includes interface circuitry to receive signals including video signals and drawing commands, and a command interpreter to receive the drawing commands and provide on screen display (OSD) signals in response to the drawing commands. Video processing circuitry processes the received video signals to provide processed video signals, and a blender to blend the OSD signals and the processed video signals to produce blended video signals including the OSD signals and the processed video signals. Other embodiments are described and claimed.

On screen displays associated with remote video source devices

A system including a receiver, a TMDS link (or other serial link), and a transmitter configured to transmit K-bit video words (typically, encoded 8-bit video words) over the link. In typical embodiments, the transmitter is configured to pack a sequence of N-bit video words, where N&#x2260;K (e.g., N=10, 12, or 16, when K=8) into a sequence of K-bit fragments, encode the fragments, and transmit the encoded fragments. The transmitted data are indicative of a sequence of M-fragment groups, and the transmitter is typically configured also to transmit over the link packing phase data indicative of the phase of the most recently transmitted fragment. Other aspects are transmitters and receivers for use in such a system and methods implemented by any such transmitter, receiver, or system.

Method and system for transmitting or receiving N-bit video data over a serial link

Method and system for transmitting N-bit video data over a serial link

In a class of embodiments, the invention is an open computing system (e.g., a PC) in which a protected, closed subsystem is embedded. The closed subsystem typically includes multiple parts that ensure that content protection keys and protected content are never revealed outside the closed subsystem. Content (e.g., high-definition digital video) that enters the closed subsystem (and is typically decrypted and re-encrypted within the closed subsystem) is afforded a similar level of protection within the open system as can be obtained in standalone closed systems. Other aspects of the invention are methods for protecting content within an open computing system, a closed system (or disk drive thereof) configured to be embedded in an open computing system, and circuitry configured to be embedded in an open computing system for combining the output of a closed subsystem with other output (e.g., graphics and/or audio output) of the open computing system.

Method and apparatus for content protection within an open architecture system

A system and a method for improving magnified texture-mapped pixel performance in a single-pixel pipeline. A plurality of textured pixel addresses corresponding to a plurality of pixels may be generated. A FIFO or other memory unit may be used to linearly order the plurality of textured pixel addresses. Two consecutive textured pixel addresses out of the plurality of textured pixel addresses may be examined if they map to a common set of texels in texture space. The two consecutive textured pixel addresses may be merged together and propagated down the pipeline if they map to the common set of texels. However, only a first of the two consecutive textured pixel addresses may be propagated down the pipeline if the two consecutive textured pixel addresses do not map to a common set of texels. Texel data may be generated in response to receiving either the combined texel structure or the first of the two textured pixel addresses. The texel data may be filtered using one or more texture filters in order to generate texture values. The next two textured pixel addresses that may be examined by the merge unit include the subsequent two consecutive textured pixel addresses, or a second of the two consecutive textured pixel addresses and a subsequent consecutive textured pixel address.

Magnified texture-mapped pixel performance in a single-pixel pipeline

A system and method are disclosed for rendering polygons. Parameter values may be rendered for only one sample position of a plurality of neighboring sample positions within a polygon. The parameter values rendered for the one sample position may then be transmitted to one or more memories and conditionally stored in a plurality of memory locations that correspond to the plurality of neighboring sample positions. Transmitting parameter values to one or more memories may be achieved in a single transaction. Depth values may be rendered for each sample position in the plurality of neighboring sample positions. Depth value data may be compressed. In some embodiments, the one or more memories may be configured to determine depth values for each of the neighboring sample positions.

Sample replication mode with depth value calculation

A graphical processing system comprising a computational unit and a shadow processing unit coupled to the computational unit through a communication bus. The computational unit is configured to transfer coordinates Cof a point P with respect to a first space to the shadow processing unit. In response to receiving the coordinates C, the shadow processing unit is configured to: (a) transform the coordinate Cto determine map coordinates s and t and a depth value Dfor the point P, (b) access a neighborhood of depth values from a memory using the map coordinates s and t, (c) compare the depth value Dto the depth values of the neighborhood, (d) filter binary results of the comparisons to determine a shadow fraction, and (e) transfer the shadow fraction to the computational unit through the communication bus.

System and method for computing filtered shadow estimates using reduced bandwidth

An external cache management unit for use with 3D-RAM and suitable for use in a computer graphics system is described. The unit maintains and tracks the status of level one cache memory in the 3D-RAM. The unit identifies dirty blocks of cache memory and prioritizes block cleansing based on a least used algorithm. Periodic block cleansing during empty memory cycles is provided for, and may also be prompted on demand.

Active block write-back from SRAM cache to DRAM

A rendering unit positions a supertile so that it intersects a primitive. The rendering unit repeatedly walks over bins of the supertile, applying a layer of texture to the bins of the supertile in each iteration of said repeated walking. The rendering unit advances to the next texture layer after having applied the current texture layer to each candidate bin of the supertile. The results of each texture layer application to the bins may be stored in a texture accumulation buffer. The size of the supertile corresponds to the size of the texture accumulation buffer. After applying a last layer of texture to the bins of the supertile, the supertile may be advanced to a new position. The rendering unit traverses the primitive with the supertile so that the union of areas visited by the supertile covers the primitive.

Multi-texturing by walking an appropriately-sized supertile over a primitive

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Saratoga, CA, United States of America

Michael G Lavelle