Freescale Semiconductor,inc.

Motorola Corporation

Silicon Laboratories Inc.

Michael G Khazhinsky

James W Miller

Michael A Stockinger

Leo Mathew

Byoung W Min

Laegu Kang

Melanie Etherton

Jeremy Charles Smith

Ravi Kishore Kummaraguntla

Fujio Takeda

Valery Neiman

Geoffrey B Hall

Aykut Dengi

William E Moore

Eyal Melamed-Kohen

Joseph Y Chan

Jose A Camarena

Anirudh Oberoi

Martin J Bayer

James C Weldon

Bryan D Preble

A balun includes an input coil and an output coil with first and second outputs that vary during normal operation. The output coil has a center point connection that remains substantially constant during normal operation. An ESD circuit provides a low impedance path between the center point connection and chip ground when the voltage at the center point connection is above a first threshold voltage or below a second threshold voltage and isolates the center point connection from chip ground otherwise. Another ESD protection circuit provides ESD protection for other input or output terminals of the integrated circuit by selectively coupling the other input or output terminals to chip ground. Thus, a charge that builds up between one of the balun outputs and another terminal on the integrated circuit can be safely dissipated.

Electrostatic discharge protection for a transformer balun

Diode circuit layout topologies and methods are disclosed that exhibit reduced lateral parasitic bipolar characteristics at lateral parasitic bipolar circuit emitter edges during ESD or other voltage events as compared to conventional circuit layout topologies. The disclosed diode circuit layout topologies may be implemented to recess parasitic emitter ends relative to surrounding well ties, for example, to reduce or substantially eliminate parasitic bipolar action at lateral emitter edges of the circuitry during ESD events so as to provide higher current threshold for device failure, allowing for smaller device area and/or improved ESD robustness for a given circuit device.

Diode circuit layout topology with reduced lateral parasitic bipolar action

An eFuse (electronic fuse) circuit has a first detector for determining whether an ESD (electrostatic discharge) event occurs at a circuit pad of an integrated circuit and provides an ESD trigger signal in response thereto. A second detector detects a presence of a first power supply voltage and provides a power on signal indicating the presence of the first power supply voltage. A fuse is permitted to be programmable when no detection of the ESD event occurs and at the same time a presence of the power on signal is detected. The fuse is not permitted to be programmed when an ESD event is detected or when there is an absence of the power on signal. An array of fuses is thereby protected from inadvertent programming from an ESD event or powering up an integrated circuit.

Method and circuit for eFuse protection

An electrostatic discharge (ESD) protected circuit is coupled to a power supply voltage rail and includes a multiple independent gate field effect transistor (MIGFET), a pre-driver, and a hot gate bias circuit. The MIGFET has a source/drain path coupled between an output pad and the power supply voltage rail and has a first gate terminal and a second gate terminal. The pre-driver circuit has an output. The hot gate bias circuit is coupled to the first gate terminal of the MIGFET, and the output of the pre-driver circuit is coupled to the second gate terminal of the MIGFET. The hot gate bias circuit is configured to apply a bias voltage to the first gate terminal of the MIGFET during an ESD event that increases the breakdown voltage of the MIGFET so as to better withstand the ESD event.

MIGFET circuit with ESD protection

Circuitry on integrated circuits usually includes protection against electrostatic discharge (ESD) events. A second ESD current path may be provided in addition to a first ESD current path for shunting ESD current away from circuitry to be protected during an ESD event. In addition to the standard power and ground buses used to provide power and ground voltages to the protected circuitry, one or more extra power and/or ground buses and associated circuitry may be added for improved ESD protection.

Electrostatic discharge circuit and method therefor

An integrated circuit () includes first and second power domains and a bank of input/output (I/O) cells () coupled to the first and second power domains. The bank of I/O cells () includes a first plurality of active clamps () for the first power domain and a second plurality of active clamps () for the second power domain wherein the first () and second () pluralities of active clamps overlap along the bank of I/O cells. According to one aspect each of the plurality of input/output cells () has a bonding pad () for receiving an output signal referenced to a respective first power domain, and at least one ESD protection element () for a respective second power domain. According to another aspect, each of the plurality of input/output cells () has a bonding pad () for receiving a respective output signal and at least one ESD protection element for each of a first power domain and a second power domain.

Electrostatic discharge (ESD) protection circuit for multiple power domain integrated circuit

An integrated circuit includes a first I/O cell disposed at a substrate, the first I/O cell including a first electrostatic discharge (ESD) clamp transistor device. The first ESD clamp transistor device includes a control electrode, a first current electrode coupled to a first voltage reference bus, and second current electrode coupled to a second voltage reference bus. The first ESD clamp transistor device has a first channel width. The integrated circuit further includes a second I/O cell including a second ESD clamp transistor device. The second ESD clamp transistor device includes a control electrode, a first current electrode coupled to the first voltage reference bus, and second current electrode coupled to the second voltage reference bus. The second ESD clamp transistor device has a second channel width different than the first channel width.

Distributed electrostatic discharge protection circuit with varying clamp size

An electronic device can include a gated diode, wherein the gated diode includes a junction diode structure including a junction. A first conductive member spaced apart from and adjacent to the junction can be connected to a first signal line. A second conductive member, spaced apart from and adjacent to the junction, can be both electrically connected to a second signal line and electrically insulated from the first conductive member. The junction diode structure can include a p-n or a p-i-n junction. A process for forming the electronic device is also described.

Electronic device including a gated diode

A method for making a semiconductor device is provided herein. In accordance with the method, a semiconductor stack is provided which includes a semiconductor substrate, a first semiconductor layer, and a first dielectric layer disposed between the substrate and the first semiconductor layer. A first trench is formed in the first dielectric layer which exposes a portion of the substrate, and a first implant region is formed in the first trench. Cathode and anode regions are formed in the first implant region.

Area diode formation in SOI application

An ESD protection system for I/O cells of an integrated circuit. The I/O cells of a bank of cells include a first type of I/O cells having ESD trigger circuits and a second type of I/O cells having ESD clamp devices. In one embodiment, the ESD trigger circuits of the first type are located at the same area of an active circuitry floor plan as the area in the floor plan for the ESD clamp devices of the I/O cells of the second type.

I/O cell ESD system

Electronic device and a process for forming the electronic device

A rail clamp circuit () includes first and second power supply voltage rails, a multiple independent gate field effect transistor (MIGFET) (), and an ESD event detector circuit (). The MIGFET () has a source/drain path coupled between the first () and second () power supply voltage rails, and first and second gates. The ESD event detector circuit () is coupled between the first () and second () power supply voltage rails, and has first and second output terminals respectively coupled to the first and second gates of the MIGFET. In response to an electrostatic discharge (ESD) event between the first () and second () power supply voltage rails, the ESD event detector circuit () provides a voltage to the second gate to lower an absolute threshold voltage of the MIGFET () while providing a voltage to the first gate above the absolute threshold voltage so lowered, thereby making the MIGFET () conductive with relatively high conductivity.

Integrated circuit with multiple independent gate field effect transistor (MIGFET) rail clamp circuit

An ESD protection circuit () and a method for providing ESD protection is provided. In some embodiments, an N-channel transistor (), which can be ESD damaged, is selectively turned on and made conducting. The purpose of turning on the N-channel transistor () is to maximize the Vt1 of the N-channel transistor (). Vt1 is the drain-to-source voltage point at which the parasitic bipolar action of the N-channel transistor () first occurs. In some embodiments, the ESD protection circuit () includes a diode () which provides an additional current path from the I/O padto a first power supply node ().

A method for making a semiconductor device is provided. The method comprises (a) providing a semiconductor stack comprising a semiconductor substrate (), a first semiconductor layer (), and a first dielectric layer () disposed between the substrate and the first semiconductor layer; (b) forming a first trench in the first dielectric layer which exposes a portion of the substrate; (c) forming a first doped region () in the exposed portion of the substrate; and (d) forming anode () and cathode () regions in the first implant region.

Growing community of inventors

Austin, TX, United States of America

Michael G Khazhinsky