Motorola Corporation

Other

Michael G Gallup

L Rodney Goke

Robert W Seaton, Jr

Terry G Lawell

Stephen G Osborn

James G Gay

William B Ledbetter, Jr

Thomas J Tomazin

Michael F Wiles

Erik L Welty

Kenneth C Scheuer

Steven C McMahan

Meltin Bell

Jack R Davis

Steven Craig McMahan

Kuppuswamy Raghunathan

Kevin L McLaughlin

Brian F Wilkie

Philip S Smith

Ralph C McGarity

Bernard C Dewitt

John Suchyta

Russell Stanphill

A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Data processing system and method thereof

A data processor has at least one output terminal which a user of the data processor can vary the output impedance thereof depending upon the application environment of the data processor. A first output buffer of an output buffer stage has a predetermined output impedance and is coupled between an input of the stage and the output terminal. The first output buffer provides a first output terminal impedance. A second output buffer having a lower output impedance than the first output buffer may be selectively coupled in parallel to the first output buffer to reduce the output impedance of the output terminal. The coupling of the output buffers is controlled by a user of the data processor who provides a control input for selecting one of a plurality of predetermined output terminal impedance values.

Data processor having an output terminal with selectable output

Method and apparatus for performing a vector skip instruction in a data

A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands. The data processing system (55) includes a plurality of instructions which include and utilize an extension bit during execution. In one embodiment, a plurality of instructions, both arithmetic and non-arithmetic, use extension bits for preliminary and non-preliminary instructions in order to accommodate large data widths.

Instruction in a data processing system utilizing extension bits and

A data processor for storing vector data in multiple locations within the processor using a pointer value and a mask value. In one embodiment, a multi-entry input data register is used to receive input data to be provided to a plurality of processing elements. A pointer value is used to address the multi-entry input data register. A mask value may be used to provide the same data to a plurality of locations within the input data register.

Method and apparatus for storing vector data in multiple non-consecutive

Saturation instruction in a data processor

A method and apparatus for providing bus protocol simulation in a multi-processor data processing system (10). A plurality of edge interface circuits (14,16) are used to interface a first bus (32, 34, 36), which uses a first bus protocol, with a plurality of data processors (50-65), each of which uses a second bus protocol. A memory (90) within each edge interface circuit (14,16) is loaded with a plurality of values. Each of the plurality of values has a control portion and a data portion. The control portion of memory entry 'N' is used to initiate the transfer of the data from memory entry 'N+1'. In an alternate embodiment, multi-processor data processing system (210) includes a plurality of data processors (250-258) and a plurality of edge interface circuits (214-217).

Method and apparatus for providing bus protocol simulation

Data processor for performing a comparison instruction using selective

A method for complex data movement in a multi-processor data processing system. In one embodiment, the multi-processor data processing system (10) includes an array (12) of data processors (50-65), a plurality of edge interface circuits (14,16), and a bus interface controller (22). In an alternate embodiment, multiprocessor data processing system (210) includes an array (212) of data processors (250-258), a plurality of edge interface circuits (214-217), and a bus interface controller (222). The data processing systems (10,210) are capable of performing complex data movement patterns between the processors (50-65,250-258) and the corresponding edge interface circuits (14, 16, 214-217), such as a transpose pattern, a ping-pong pattern, and a checkerboard pattern.

Method for complex data movement in a multi-processor data processing

Data processor for conditionally modifying extension bits in response to

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Austin, TX, United States of America

Michael G Gallup