Apple Inc.

Pixim, Incorporated

Ati International Srl

Ati Technologies Inc.

Advanced Micro Devices Corporation

Arteris, Inc.

Other

Globalfoundries Inc.

Ati Technologies Ulc

Michael G Frank

Date Jan Willem Noorlag

Ricardo Jansson Motta

Santiago Fernandez-Gomez

Jeffrey E Frederiksen

William R Bidermann

Robert Laker

Mohammed Khaleeluddin

Aki Niimura

Arkadi Avrukin

James B Keller

Korbin S Van Dyke

Erik P Machnicki

David I J Glen

Gurjeet S Saund

Wolfgang Roethig

David Xiao Dong Yang

Adrian Sfarti

Odutola Oluseye Ewedemi

Justin Reyneri

Steven Charles Dilliplane

Biljana D Simsic

Zaw Min Soe

Jerrold Von Hauck

Brijesh Tripathi

Gordon Caruk

Benoit De Lescure

Ulrich Tobias Barnhoefer

Anup K Sharma

Jean-Didier Allegrucci

David A Strasser

Richard J Selvaggi

Michael Haertel

David Daming Kuo

Ranganathan Sudhakar

Hui Tian

Kuldip Sahdra

Patrick D McNamara

Albert C Kuo

Gary W Root

Benjamin P Olding

Sasa Marinkovic

Jianlin Yu

Debjit DasSarma

David Leibs

James B Fry

John Raymond Wiseman

Ed Callway

Paul E Kalapathy

Jamil Ahmed

System and methods are disclosed for aggregating identical requests sent to a target from multiple initiators through a network-on-chip (NoC). The requests are marked for aggregation. The NoC uses request aggregators (RA) as an aggregation point to aggregate the identical requests that are marked for aggregation. At the aggregation point, the identical requests are reduced to a single request. The single request is sent to the target. The process is repeated in a cascaded fashion through the NoC, possibly involving multiple request aggregators. When a response transaction is received back from the target, which is at the aggregation point closest to the target, the response transaction is duplicated and sent to every original requester, either directly or through other request aggregators, which further duplicate the already duplicated response transaction.

System and method for performing transaction aggregation in a network-on-chip (NoC)

A cache coherent interconnect connected to one or more agents, such as CPUs, GPUs, Peripherals, etc. using network interface units (NIUs), and having one or more internal modules, such as a directory, is provided with one or more event-to-message converters, and one or more message-to-event converters. When a particular event occurs within one of the agents or modules, a message is initiated and transmitted using the existing interconnect wiring to one or more agents or modules, which have associated NIUs, that need to be aware of the event. Response messages showing the status of the event-message may also be generated. Therefore, messages are sent when events occur, instead of constantly using bandwidth for status updates when no status is changing, making the interconnect more efficient and freeing up bandwidth. These converters are provided as additional hardware blocks incorporated into the various NIUs and modules.

System and method for event messages in a cache coherent interconnect

A cache coherent interconnect connected to one or more agents, using Network Interface Units (NIUs), and also having one or more internal modules, such as a directory, is provided with one or more message builders and message receivers. These message builders and message receivers are provided as additional hardware IP blocks incorporated into the various NIUs and modules. When an agent signals an intention to enter/exit the cache coherent interconnect, a message communicating this information is generated using message builders, and transmitted using the interconnect wiring as a 'virtual wire' to one or more message receivers associated with directories that need to be aware of the entry/exit transition of the agent. The directories are provided with tracking engines to manage the entry/exit information and status of the agent. Interconnects may include a broadcast engine to provide distribution to, and aggregate acknowledgements from, a single source to multiple destinations.

System and method to enter and exit a cache coherent interconnect

A quality of service (QoS) management system and guarantee is presented. The QoS management system can be used for end to end data. More specifically, and without limitation, the invention relates to the management of traffic and priorities in a queue and relates to grouping transactions in a queue providing solutions to queue starvation and transmission latency.

Queue management system, starvation and latency management system, and methods of use

An age compensation method and apparatus for an integrated circuit (IC). An IC may be configured to operate at an initial operating voltage at the beginning of its operational life. Various circuits may be used to detect aging of the IC, and indications of aging may be stored to determine the aging of the IC. The information indicative of the determined aging of the IC may be compared to an aging threshold. If the information indicates that the aging is greater than or equal to the determined aging threshold, the operating voltage of the IC may be increased. This process may be repeated over the life of the IC, increasing the operating voltage as the IC ages. Raising the operating voltage in response to aging may compensate for various age related degradation mechanisms that can occur over the operational life of the IC.

Compensating for aging in integrated circuits

A digital processor for recovering a source bitstream from an encoded bitstream that has been encoded according to a context adaptive binary arithmetic coding (CABAC) algorithm. The processor includes a first execution unit and a second execution unit. The first execution unit generates first execution data by operating on a first register and a second register, and stores the first execution data in the first register. The first execution data includes a current output bit, a temporary range value and a temporary offset value. The current output bit corresponds to a bit of the source bitstream. The second execution unit generates second execution data by operating on the first register and the second register, and stores the second execution data in the second register. The second execution data includes a normalized range value and a normalized offset value.

Execution units for implementation of context adaptive binary arithmetic coding (CABAC)

A system and method of generating a high dynamic range image. A single reset of an image sensor may be executed followed by two or more reads of the sensor to retrieve data. These reads of the image sensor may be done prior to a subsequent reset of the sensor. These reads may also be accomplished at predetermined times relative to one another. Data read out during these scans may be deinterleaved by an image signal processor and combined into a high dynamic range image.

Image sensor having HDR capture capability

Devices and methods for obtaining image data that preserves highlight details and shadow details from image data from a high dynamic range (HDR) image sensor are provided. For example, an image signal processor may include a first data path of a relatively high bit depth, front-end image processing logic, and a second data path of a relatively low bit depth. The first data path may receive HDR image data from an image sensor. The front-end image processing logic may convert the HDR image data into lower-bit-depth image data, while preserving highlight details and/or shadow details of the HDR image, by using at least two transfer functions that preserve different subsets of the high dynamic range. The second data path may output this lower-bit-depth image data to other image processing logic for additional image processing.

Devices and methods for obtaining high-local-contrast image data

In an embodiment, a compression unit is provided which may perform compression of a pixel stream. Similarly, a decompression unit may be provided which may decompress the compressed pixel stream. The compression and decompression units may include a streaming wavelet transform, which may perform the wavelet transform through a pipeline of wavelet operations. Each section of the pipeline may perform a pass of the wavelet transform on the pixel stream, and the section may provide input to another section of the pipeline that performs a next pass of the wavelet transform. The transform may thus be performed on the fly as the pixels are received.

Streaming wavelet transform

Techniques are disclosed relating to detecting a voltage change. In one embodiment, an integrated circuit may include a monitor circuit and a power management unit. The power management unit may be configured to request a voltage change. The monitor circuit may be configured to detect the requested voltage change and to provide an indication that the voltage change is complete. In response to the indication that the voltage change is complete, the power management unit may adjust a clock frequency.

Voltage detection

In an embodiment, a compression unit is provided which may perform compression of images with low latency and relatively little hardware. Similarly, a decompression unit may be provided which may decompress the images with low latency and hardware. In an embodiment, the transmission of compressed coefficients may be performed using less than two passes through the list of coefficients. During the first pass, the most significant coefficients may be transmitted and other significance groups may be identified as linked lists. The linked lists may then be traverse to send the other significance groups. In an embodiment, a color space conversion may be made to permit filtering of fewer color components than might be possible in the source color space.

Memory compression technique with low latency per pixel

Devices and methods for dynamic dithering are provided. For example, an electronic device according to an embodiment may include image processing circuitry that operates on higher-bit-depth image data and a display panel that displays lower-bit-depth image data. To obtain the lower-bit-depth image data, the image processing circuitry may perform dynamic dithering on the higher-bit-depth image data. Such dynamic dithering may involve dithering frames of the higher-bit-depth image data based at least in part on respective rounding threshold values.

Devices and methods for dynamic dithering

An apparatus and method for changing the extra margin adjustment (EMA) for a memory is disclosed. A control unit may access a table responsive to an indication of a change of operating point. The table includes a number of different delay times, each of which corresponds to a particular operating point. The control unit may select the delay time that corresponds to the new operating point to which the memory operation is being changed. The control unit may further convey an indication of the selected delay time to the memory, thereby causing the memory to operate according thereto.

Memory read timing margin adjustment for a plurality of memory arrays according to predefined delay tables

Adjusting a phase locked loop (PLL) clock source to reduce wireless communication (e.g., radio frequency (RF)) interference within a device. The PLL may be included in a high speed serial interface, e.g., coupled to a display, and may be initially driven by a first clock. Later, when a second clock is available and aligned with the first clock, the PLL may be driven by the second clock. The second clock may be configured to change its frequency over time such that the PLL does not lose lock and also does not interfere (or reduces interference) with wireless communication of the device. For example, the second clock may be programmable or may dynamically vary its operating frequency, thereby reducing its interference with the wireless communication of the device.

Switching a PLL clock source to reduce wireless communication interference

The present disclosure relates to the use of inverse dithering of color or grey-scale images. In certain embodiments, an image area may be selected having a center pixel. A predictive value of the image area may be found by averaging the values of the pixels in the image area. This predictive value may be compared to the center pixel's real value. A difference between the real value and the predictive value may then be found and used to diffuse the energy removed from the center pixel to neighboring pixels. By inverse dithering images using an energy diffusion approach, the images may be presented as having a more visually appealing display, even in situations where the images may undergo further edge enhancements.

Method and apparatus to increase bit-depth on gray-scale and multi-channel images (inverse dithering)

Growing community of inventors

Fairfield, CT, United States of America

Michael G Frank