Lattice Semiconductor Corporation

Michael G France

Ludmil Nikolov

Robert M Bartel

Ji Zhao

Kent R Callahan

Harald Weller

Trent Whitten

A method of providing a clock signal for an embodiment includes performing a calibration for a closed loop control system to determine a control signal value that provides a desired tuning of the closed loop control system. The control signal value is stored and provided to a delay circuit, wherein a delay range and a delay step size of the delay circuit is based on the control signal value. A delay select control signal is provided to the delay circuit to select a specific delay within the delay range.

Clock delay and skew control systems and methods

In one example, a method of tuning an oscillator of a phase-locked loop (PLL) circuit includes adjusting a coarse control signal to select one of a plurality of frequency tuning curves of the oscillator. The method includes adjusting a fine control signal to select a position on the selected frequency tuning curve. A frequency of the oscillator is determined by the coarse control signal and the fine control signal. The method includes attempting to detect a lock between a feedback signal and a reference signal. A frequency of the feedback signal is determined by the frequency of the oscillator. The method includes comparing the fine control signal to a reference value if the lock is detected. The method includes adjusting the coarse control signal to select a different one of the frequency tuning curves if the selected position on the selected frequency tuning curve is outside a desired tuning range.

Oscillator tuning for phase-locked loop circuit

In one embodiment, a method is provided for measuring a dynamic phase offset between a PLL's input clock and the PLL's feedback input clock, wherein the input clock is spread spectrum modulated in a spread spectrum mode and is not modulated in a static mode. The method includes: in the spread spectrum mode, measuring phase jitter between the input clock and the feedback input clock to form a spread spectrum phase jitter measurement; in the static mode, measuring phase jitter between the input clock and the feedback input clock to form a static phase jitter measurement; and comparing the spread spectrum phase jitter measurement to the static phase jitter measurement to determine the dynamic phase offset.

Dynamic phase offset measurement

In accordance with one or more embodiments of the present invention, a system includes a phase-locked loop circuit that receives a reference signal and a feedback signal and provides an output signal. A control circuit also receives the reference signal and the feedback signal and provides a correction current for the phase-locked loop circuit to reduce a phase error of the output signal.

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Austin, TX, United States of America

Michael G France