Advanced Micro Devices Corporation

Michael G Drake

Richard William Schuckle

Andrew W Steinbach

Joe A Ricks

Chris Tressler

Greg Schelling

Edward Guerrero

John Bennett

K Vincent Bridgers

A printed circuit board assembly with improved bypass decoupling for BGA packages. In one embodiment, a capacitor may be interposed between a BGA package and a PCB within a perimeter of the contact pads that form a BGA footprint. The capacitor may have physical dimensions which allow a BGA package to be mounted such that there is no physical contact between the capacitor and the BGA.

Printed circuit board assembly with improved bypass decoupling for BGA packages

A system and method are presented for transmitting data upon an address portion of a computer system bus during periods of maximum or near-maximum utilization of a data portion of the bus. One embodiment of the computer system includes at least one central processing unit (CPU) and a main memory coupled to a processor bus. The main memory stores data, and the CPU executes instructions stored within the main memory. The processor bus is a split transaction bus. The processor bus is divided into an address bus, a data bus, and a control bus including address, data, and control signal lines, respectively. The CPU and the main memory each include a bus interface, and are coupled to the processor bus via the bus interface. The bus interface includes a transaction queue coupled to an interface unit. The interface unit is coupled to the address, data, and control buses, and performs bus transactions (i.e., read and/or write transactions) upon the processor bus. The split bus transactions are coordinated using tag values generated by the CPU. The transaction queue stores a list of pending data exchange operations. Each interface unit competes for control of the address and data buses. When the transaction queue is not full, the interface unit performs data transfers using the data bus. When the transaction queue is full (e.g., when the data bus is nearing maximum utilization), the interface unit is configured to gain control of the address bus and to transfer data via the address bus.

System and method for transmitting data upon an address portion of a

A computer system including a processor, a main memory and a cache memory uses tagging of various regions of memory to define and select caching properties of transfers between the processor and memory via the cache. The main memory contains not only standard random access memory (RAM) and read-only memory (ROM) but also memory-mapped input/output (I/O) sources. Tagging of the memory regions configures the regions for association with a particular set of caching properties. For example, a memory-mapped video I/O buffer may be tagged with a MM.sub.-- IO.sub.-- VBUF tag designating the caching properties of write-back cacheability with weak read/write ordering. Low-level operating system software, such as the Hardware Abstraction Language (HAL) interface of the Windows NT.TM. operating system or device driver software, initialize the memory regions, the cache and make symbolic associations between the memory regions and the cache. The cache, operating as directed by the memory tags, allows read and write operations that are used for performing various types of multimedia or signal processing operations including decompression, drawing operations, compression, mixing, and the like, which are performed on a virtually-cached multimedia drawing surface. The data for performing the multimedia or signal processing operations are either already located on the I/O surface or read from another storage location local to the processor or from an external processor, which is also cached and tagged as a special cached region. The processor executes operations acting on the cached data. When all operations are completely executed by the processor, only the cached memory regions are flushed using a flush instruction such as CFLSH�MM.sub.-- IO.sub.-- VBUF!. The flush instruction directs the cache to write back and invalidate the regions having the designated tag, here MM.sub.-- IO.sub.-- VBUF.

Cache system and method using tagged cache lines for matching cache

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Austin, TX, United States of America

Michael G Drake