Adv Antest Corporation

Credence Systems Corporation

Activision Publishing, Inc.

Michael Frank Jones

Alan S Krech, Jr

Eric Kushnick

William A Fritzsche

Brian McClendon

Richard Daniel Webb

Edmundo DeLaPuente

Christopher C Tanner

Burnell G West

Edmundo De La Puente

Mei-Mei Su

Srdjan Malisic

Chi Yuan

Ben Rogel-Favila

David Eskeldson

Duane Champoux

Takahiro Yasui

Linden Hsu

Jamie S Cullen

Alan S Krech

Xinguo Zhang

Ken Hanh Duc Lai

Darrin Paul Albers

Frederic Giral

Robert Whyte

Remi Simon Vincent Arnaud

Taichi Fukuda

Scott Bloom

Frederick Giral

Remi Simon Vincent Amaud

Naveed Zaman

Yann Gazounaud

An automated test equipment (ATE) apparatus comprises a computer system comprising a system controller, wherein the system controller is communicatively coupled to a tester processor and an FPGA. The tester processor is operable to generate commands and data from instructions received from the system controller for coordinating testing of a device under test (DUT), wherein the DUT supports a plurality of non-standard sector sizes and a plurality of protection modes. The FPGA is communicatively coupled to the tester processor, wherein the FPGA comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing the DUT, and wherein the at least one hardware accelerator circuit is able to perform computations to calculate protection information associated with the plurality of protection modes and to generate repeatable test patterns sized to fit each of the plurality of non-standard sector sizes.

Automated test equipment (ATE) support framework for solid state device (SSD) odd sector sizes and protection modes

A method for diagnosing a root cause of failure using automated test equipment is disclosed. The method comprises monitoring data traffic associated with testing a device under test (DUT) in the automated test equipment using a plurality capture modules, wherein the plurality of capture modules are programmed onto a programmable logic device, wherein the programmable logic device is controlled by a system controller and is operable to generate commands and data to test the DUT, wherein the plurality of capture modules are operable to selectively capture the data traffic to be monitored, and wherein the data traffic monitored comprises a flow of traffic between the DUT and the system controller. The method further comprises saving results associated with the monitoring in respective memories associated with each of the plurality of capture modules. Further, the method comprises transmitting the results upon request to an application program executing on the system controller.

Traffic capture and debugging tools for identifying root causes of device failure during automated testing

A programmable logic device, such as a field programmable gate array (FPGA), is disclosed that allows for both high speed and low speed signal processing using the existing high speed transceiver. The programmable logic of the device may be programmed to include a sampling logic block that determines the low speed bit patterns from a device under test (DUT). The logic may further include a bit replication logic block that replicates bits such that the output of the device's high speed transceiver looks like a low speed signal to the DUT. The device, therefore, can communicate with the DUT at both the high and low speeds without the need for intermediate hardware.

Method and apparatus to provide both high speed and low speed signaling from the high speed transceivers on an field programmable gate array

An ATE system performs RA over NAND flash memory DUTs. A first UBM captures fresh failure related data from a DUT. A second UBM transmits existing failure related data. A fail engine accesses the stored existing failure related data and generates a failure list based thereon. The storing and the accessing the existing failure related data, and/or the generating the failure list, are performed in parallel contemporaneously in relation to the capturing the fresh data. The generated failure list is queued. A failure processor, which may be operable for controlling the capturing, computes a redundancy analysis based on the queued failure list. The first and second UBMs then ping-pong operably.

Testing memory devices with parallel processing operations

In a testing device, a method for implementing efficient interrupt routing. The method includes receiving an interrupt from a plurality of interrupt causes, consulting an interrupt routing table to determine an output interrupt vector, and forwarding the output interrupt vector to one or more of a plurality of different CPUs in accordance with the interrupt routing table.

Flexible interrupt generation mechanism

A system for testing a device under test (DUT) includes a test controller unit that includes a first memory operable to store a data pattern; a bridge circuit that includes a second memory that is smaller than the first memory, and a functional unit that includes a third memory that is smaller than the second memory. Portions of the data pattern are selectively transferred from the first memory to the second memory during and for DUT testing operations. The functional circuit interfaces with the DUT for testing. Portions of the data pattern are selectively transferred from the second memory to the third memory for application to the DUT.

Staged buffer caching in a system for testing a device under test

A method for performing test site synchronization within automated test equipment (ATE) is presented. The method comprises controlling a plurality of test program controllers (TPCs) using a plurality of bridge controllers (BCs), wherein each TPC can initiate multiple asynchronous events. For an asynchronous event initiated by a TPC, raising a busy flag while the asynchronous event is not yet complete and de-asserting the busy flag when the asynchronous event is complete, wherein the asynchronous event corresponds to a task requiring an indeterminate amount of time. It also comprises generating a busy signal in the first BCs in response to receiving a busy flag from any of the plurality of TPCs, wherein the busy signal remains asserted while any of the plurality of TPCs asserts a busy flag. Finally, it comprises transmitting the busy signal to the plurality of TPCs, wherein the TPCs use the busy signal to synchronize operations.

Flexible test site synchronization

In a testing device, a method for implementing distributed pin mapping. The method includes receiving a request from a plurality of CPUs to access a pin map memory at each of a plurality of bridges, implementing accesses to the pin map memories locally at each of the plurality of bridges, and using pin map data from the accesses to the plurality of CPUs to enable access to testing device resources.

Distributed pin map memory

Serial input devices (e.g., pin electronics modules) are coupled to an interface via data lines, clock lines, and select lines. A first subset and a second subset of the devices are each arrayed in columns, rows, and layers. Each data line is coupled to a respective row in the first subset and a respective row in the second subset; each clock line is coupled to a respective column in the first subset and a respective column in the second subset; and each layer in each subset is coupled to a respective select line. The interface can program a device by concurrently activating one of the data lines, one of the clock lines, and one of the select lines.

Programming multiple serial input devices

A system and method is presented that leverages independent innovation in entertainment content and graphics hardware. In this system and method, the current image generation run-time application is replaced with a new framework defining the connectivity, features, and behavior necessary to implement a graphics system. All this takes place in the context of a software platform utilizing a late-integration mechanism that dynamically integrates the various real-time components in a run-time application. Ultimately displacing hardware as the central focus of development efforts, this software platform functionally is the graphics application, at least as viewed by the simulation host computer, database developers, and those responsible for visual system procurement and maintenance. An innovative software architecture, the Graphical Application Platform (GAP) is presented. The GAP builds on image generator, workstation, and scene graph success by extending the concepts of platform and framework into the real-time graphics domain&#x2014;bridging the gap between image generation concerns and contemporary hardware and software realities by decoupling content, hardware and applications. This new approach also provides technology to address emerging concerns related to the selection and acquisition processes in the context of new low-cost, high-performance graphics hardware.

System and method for leveraging independent innovation in entertainment content and graphics hardware

Memory is divided up during the gathering of histogram data so that a portion of the memory is configured for storing the high counts expected at the minimum and maximum codes/addresses, and at least one other portion is configured for storing the lower counts expected at other codes/addresses. By configuring memory portions in this manner, memory can be more efficiently allocated.

Histogram generation with mixed binning memory

The configuration and utilization of multiple memories is disclosed to efficiently gather histogram data for either multiple devices or single devices. Each memory can be configured depending on the number of ADCs to be tested. Rather than utilizing a separate histogram engine for each ADC, or duplicate memories to test each ADC, the memory of each histogram engine can be used either for a single ADC having a large or otherwise substantial sample width, or for multiple ADCs, each having a smaller sample width. To accomplish this, the memory is partitioned into multiple segments using address decoding such that a single ADC can use all of the segments for histogram data collection, while multiple ADCs can each use one of the segments for histogram data collection.

Histogram generation with configurable memory

Dividing memory used for storing histogram data into multiple banks is disclosed to allow for phased RMW cycles. Although the same address lines are provided to each bank, address control logic ensures that each successive RMW cycle is handled by a different bank, so that another RMW cycle can be started in one bank while the previous RMW cycle is still being performed in another bank. By staggering or phasing the starts of the RMW cycles in a wraparound fashion, each histogram bin is spread out over multiple banks, but testing can proceed faster than if only a single bank was used. After the histogram data has been captured, the areas of memory in each bank associated with a particular bin can be added together to compute the total count for that bin.

Histogram generation with banks for improved memory access performance

Method and apparatus for circuit testing with ring-connected test instrument modules. A system for controlling one or more test instruments to test one or more integrated circuits includes a master clock and a controller. The test instruments are connected to form a communication ring. The master clock is connected to each test instrument and provides a clock signal to the one or more test instruments. The controller is connected to the communication ring and is configured to align counters of test instruments to derive a common clock time value from the clock signal. The controller is further configured to generate and send data words into the communication ring to carry the data words to each test instrument. The data words includes at least one data word specifying a test event to be performed, a common clock time value, and at least one of the test instruments.

Circuit testing with ring-connected test instrument modules

A method for supporting development of content independent of a run time platform is provided. A method includes storing processing blocks and storing an application graph that expresses the identity of the stored processing blocks and data connectivity therebetween. The application graph can be traversed by a graphical application platform at run time to execute appropriate blocks. A game development and run time system includes a graphical application platform that enables a game application to run on any of multiple hardware platforms. The graphical application platform has an application real time kernel, a plurality of standard features implemented as executable blocks of logic, and connections between blocks that implement data flow between the blocks. Capabilities of the game application and any of the hardware platforms can be implemented modularly by adding additional corresponding blocks and connections.

Growing community of inventors

Santa Clara, CA, United States of America

Michael Frank Jones