Texas Instruments Corporation

Michael Francis Pas

Manfred Ramin

Husam N Alshareef

Sylvia D Pas

Joseph Anthony Boduch

Robert Daniel Orr

Sandia You Ni Chiu

Mark R Visokay

Shaofeng Yu

Satyavolu Srinivas Papa Rao

C Rinn Cleavelin

Stephanie Watts Butler

Cloves Rinn Cleavelin

Zhibo Zhang

Mike Watson Goodwin

Jin-goo Park

At least some embodiments are directed to a system that comprises storage comprising a data structure that cross-references an identifier of a semiconductor wafer, a location of a die in the wafer, an identifier of a lead frame strip, a location of a lead frame in the lead frame strip, and results of a first test on the die. The system also comprises mechanical equipment configured to test packaged die. The system further comprises a processor, coupled to the storage and to the mechanical equipment, configured to perform a second test on a package containing the die and the lead frame using the mechanical equipment and the results of the first test.

Data structures for semiconductor die packaging

Semiconductor devices and fabrication methods are provided, in which fully silicided gates are provided. A lanthanide series metal is implanted into the gate electrode layer prior to silicidation and diffuses into the gate dielectric during an activation anneal. This process and resultant structure provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting transistor.

Work function adjustment with the implant of lanthanides

An orthotic device comprises a flexible support structure comprising at least one surface for contacting a body part of a user, a plurality of pressure sensors configured for coupling to a microcontroller, and a plurality of displacement regions. Each region defines a portion of said flexible support structure, wherein each portion includes at least one sensor disposed on or below the at least one surface and at least one electrically deformable unit. Each unit comprises at least one electroactive material and is configured for coupling to the microcontroller and to a power source. The device is dynamically adjustable to change its shape and support properties, when an electrical voltage is applied to the electroactive material under the control of a microcontroller.

Dynamically adjustable orthotic device

A transistor includes a semiconductor substrate includes having a gate hardmask over the gate electrode layer during the formation of transistor source/drain regions. An independent work function adjustment process implants Group IIIa series dopants into a gate polysilicon layer of a PMOS transistor and implants lanthanide series dopants into a gate polysilicon layer of a NMOS transistor.

Integration scheme for dual work function metal gates

A method for making an NMOS transistor on a semiconductor substrate includes reducing the thickness of the PMD layer to expose the polysilicon gate electrode of the NMOS transistor and the polysilicon gate electrode of the PMOS transistor, and then removing the gate electrode of the NMOS transistor. The method also includes depositing a NMOS-metal layer over the semiconductor substrate, depositing a fill-metal layer over the NMOS-metal layer, and then reducing the thickness of the NMOS metal layer and the fill metal layer to expose the gate electrodes of the NMOS transistor and the PMOS transistor.

Integration scheme for an NMOS metal gate

A method for manufacturing a semiconductor device includes forming a gate electrode over a gate dielectric. The gate dielectric is formed by forming a lanthanide metal layer over a nitrided silicon oxide layer, and then performing an anneal to inter-diffuse atoms to form a lanthanide silicon oxynitride layer. A gate electrode layer may be deposited before or after the anneal. In an embodiment, the gate electrode layer includes a non-lanthanide metal layer, a barrier layer formed over the non-lanthanide metal layer, and a polysilicon layer formed over the barrier layer. Hafnium atoms may optionally be implanted into the nitrided silicon oxide layer.

Method of forming a high-k gate dielectric layer

A chemical mechanical polishing (CMP) stop layer is implemented in a semiconductor fabrication process. The CMP stop layer, among other things, mitigates erosion of sidewall spacers during semiconductor fabrication and adverse effects associated therewith.

Sacrificial CMP etch stop layer

Semiconductor devices and fabrication methods are provided, in which fully silicided transistor gates are provided for MOS transistors. A lanthanide series metal is implanted into the gate electrode layer prior to silicidation and diffuses into the gate dielectric during an activation anneal. This process and resultant structure provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting transistor.

Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. Metal nitride is formed above a gate dielectric. A lanthaide series metal is implanted into the metal screen layer above the gate dielectric. The lanthaide metal is contained in the screen layer or at the interface between the screen metal layer and the gate dielectric. This process provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting PMOS or NMOS transistors.

Lanthanide series metal implant to control work function of metal gate electrodes

A method for manufacturing a semiconductor device. The method comprises forming a dielectric layer. Forming the dielectric layer includes depositing a silicon oxide layer on a semiconductor substrate, nitridating the silicon oxide layer to form a nitrided silicon oxide layer and incorporating lanthanide atoms into the nitrided silicon oxide layer to form a lanthanide silicon oxynitride layer.

One aspect of the invention provides a semiconductor device that includes gate electrodes comprising a metal or metal alloy located over a semiconductor substrate, wherein the gate electrodes are free of spacer sidewalls. The device further includes source/drains having source/drain extensions associated therewith, located in the semiconductor substrate and adjacent each of the gate electrodes. A first pre-metal dielectric layer is located on the sidewalls of the gate electrodes and over the source/drains, and a second pre-metal dielectric layer is located on the first pre-metal dielectric layer. Contact plugs extend through the first and second pre-metal dielectric layers.

Growing community of inventors

Richardson, TX, United States of America

Michael Francis Pas