Integrated Device Technology, Inc.

Quellan, Inc.

Michael Francis Farrell

Joy Laskar

Andrew Joo Kim

Michael Gerald Vrazel

Edward Gebara

Charles E Summers

David Anthony Stelliga

Bruce C Schmukler

Mark W Dickmann

Paul Edwin Platt

Signals propagating on an aggressor communication channel can cause detrimental interference in a victim communication channel. A signal processing circuit can generate an interference cancellation signal that, when applied to the victim communication channel, cancels the detrimental interference. The signal processing circuit can dynamically adjust or update two or more aspects of the interference cancellation signal, such as an amplitude or gain parameter and a phase or delay parameter. Via the dynamic adjustments, the signal processing circuit can adapt to changing conditions, thereby maintaining an acceptable level of interference cancellation in a fluctuating operating environment. A control circuit that implements the parametric adjustments can have at least two modes of operation, one for adjusting the amplitude parameter and one for adjusting the phase parameter. The modes can be selectable or can be intermittently available, for example.

Method and system for automatic control in an interference cancellation device

Signal transfer devices enable multiple processors to act as drivers or receivers of signals which can transition from an invalid state to a valid state and then return to the invalid state in one clock cycle. The preferred signal transfer device includes a bus line, a plurality of bus drivers electrically connected to the bus line for initiating wired-OR signal transitions and at least one self-timed booster circuit electrically connected to the bus line. The self-timed booster circuit includes a first field effect transistor electrically connected in series between the bus line and a first reference potential and a second field effect transistor electrically connected in series between the bus line and a second reference potential. A timing circuit is also provided as a plurality of inverters which are electrically coupled in series. The timing circuit, which has an input electrically coupled to the bus line, performs a boolean inversion of the signals on the bus line after a first delay. A circuit is also provided for turning on the first and second field effect transistors during consecutive time intervals which are preferably nonoverlapping to thereby reduce power consumption. Here, the circuit may comprise a multi-input NOR gate having a first input electrically connected to the output of the timing circuit, a second input electrically connected to the bus line and an output electrically connected to a gate electrode of the first field effect transistor. This circuit may also comprise an inverter having an input electrically connected to the output of the timing circuit and an output electrically connected to a gate electrode of the second field effect transistor.

Signal transfer devices having self-timed booster circuits therein

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Atlanta, GA, United States of America

Michael Francis Farrell