Ati Technologies Ulc

Advanced Micro Devices Corporation

Ati Technologies Inc.

Michael Foxcroft

George A W Guthrie

Grigori Temkine

Oleg Drapkin

Mihir Shaileshbhai Doctor

Saeed Abbasi

Krishna Sitaraman

Shirley Pui Shan Lam

Alexander Shternshain

David I J Glen

Edward George Callway

Antonio A Rinaldi

Mikhail Rodionov

Collis Quinn Carter

Nima Gilanpour

Jeffrey Herman

Thomas Y Wong

Natan Shtutman

Raymond S P Tam

Jeff Herman

Ngar Sze Nancy Chan

Mikhall Rodionov

An apparatus includes a clock circuit and a plurality of display interface circuits. The clock circuit provides a common clock signal. The display interface circuits each provide a respective display link clock signal in response to the common clock signal. One of the display link clock signals is at a different clock speed that another of the display link clock signals.

Display link clocking method and apparatus

A phase locked loop (PLL) includes a first loop, a second loop, and a lock detector. The first loop locks a feedback signal having a frequency equal to a fraction of a frequency of an output signal to a reference signal in phase. The first loop has a first bandwidth. The second loop locks the feedback signal to the reference signal in frequency and has a second bandwidth. The first bandwidth is higher than the second bandwidth. The lock detector is coupled to the second loop and increases the second bandwidth in response to detecting that the feedback signal is not locked to the reference signal.

Phase locked loop with bandwidth control

A device may generate a clock signal using spread-spectrum clocking. The spread-spectrum clocking may modulate a frequency of the clock signal to produce a plurality of frequencies for the clock signal during a modulation cycle. The device may receive an instruction to disable the spread-spectrum clocking, and may disable the spread spectrum clocking at the end of the modulation cycle.

Disabling spread-spectrum clock signal generation

A method and a phase-locked loop (PLL) for generating output clock signals with desired frequencies are described. The PLL is equipped with a ramp generator that increments or decrements a feedback divider value before providing it to a modulator. The modulator modulates the feedback divider value and provides the modulated value to a feedback divider of the PLL for performing frequency division.

Phase-locked loop frequency stepping

The loop bandwidth of a PLL is adjusted based on a difference between the output signal of the PLL and the PLL reference signal. In an embodiment, the DC open loop gain and natural frequency of the PLL are adjusted based on the phase difference between the output signal and the reference signal, so that the loop bandwidth of the PLL is increased when the phase difference is outside a programmable range and is decreased when the phase difference is within the programmable range.

Phase lock loop with adaptive loop bandwidth

A circuit includes a phase lock loop circuit and a continuous phase lock loop calibration circuit. The continuous phase lock loop calibration circuit is operatively coupled to the PLL circuit and produces a continuous calibration signal based on a reference voltage from a reference voltage circuit to calibrate the PLL circuit on a continuous basis.

Phase lock loop with continuous calibration and method therefor

A digitally programmable gain control circuit and method of operating the same is disclosed. The gain control circuit includes a programmable gain amplifier having an amplifier structure represented by a plurality of overlapping discrete monotonic transfer function segments, wherein at least one point of non-monotonicity occurs among one or more of the plurality of overlapping discrete monotonic transfer function segments, and a gain segment translator circuit operative to translate a monotonic gain value to a segment code to match the non-monotonic characteristics of the programmable gain amplifier. The programmability of the gain amplifier is provided by a coarse gain control circuit and a fine gain control circuit.

Digitally programmable gain control circuit

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Toronto, Canada

Michael Foxcroft