Altera Corporation

Michael Fitton

Kulwinder Singh Dhanoa

Mehul Mehta

Lei Xu

There is provided a processor for a base station control unit, the base station control unit being associated with a plurality of antennas; the processor comprising a plurality of processing streams, each stream being suitable for generating signals for at least one user in a plurality of users; wherein any of the processing streams can be used to generate the signals for any user in the plurality of users and for transmission by any antenna in the plurality of antennas.

Processor for a base station control unit

A ranging code present in a transmission from a transmitter to a receiver can be detected, and hence a time offset can be determined. For each of the possible ranging codes in a transmitted signal, a correlation is formed between a received signal and the ranging code for multiple subcarriers in the received signal. For multiple adjacent ranging subcarriers, the correlation is multiplied by a conjugate of the correlation of an adjacent ranging subcarrier in order to form a differential phase value. At least one ranging code in the transmitted signal can then be determined based on the differential phase values for said plurality of subcarriers. A time offset in the transmission from the transmitter to the receiver can then be determined, based on the differential phase values for the subcarriers, and based on the determined ranging code.

Ranging code detection

Embodiments of the present invention provide an apparatus and method for crest factor reduction, in which an input time domain signal is clipped to generate a clipped signal and a difference signal, and processing operations are carried out on the difference signal, before the processed difference signal is combined with the clipped signal to generate an output time domain signal.

Apparatus and method for crest factor reduction

A processor is adapted for performing a QR-decomposition. The processor has a program memory, a program controller, connected to the program memory to receive program instructions, and at least one processing unit. The processing unit includes a CORDIC calculation block, and has a distributed memory structure, with separate memory blocks for storing respective parameter values.

Methods and apparatus for matrix decompositions in programmable logic devices

A matrix decomposition circuit is described. In one implementation, the matrix decomposition circuit includes a memory, one or more memory counters to track one or more memory counter values regarding data stored in the memory, a processing unit that calculates elements of an output matrix, and a scheduler that determines an order for calculating the elements of the output matrix, where the scheduler uses one or more memory counter values to determine whether data needed for processing an element of the output matrix is available in the memory. In one specific implementation, the scheduler schedules processing of a diagonal element of the output matrix to occur as soon as the scheduler determines that each element of the output matrix needed for calculating the diagonal element is available in the memory.

Hardware architecture and scheduling for high performance solution to cholesky decomposition

In one aspect, there is provided a digital logic circuit that comprises circuitry for generating a new iteration xof the reciprocal square root of A from the previous iteration xby (i) multiplying the previous iteration xby the number A; (ii) multiplying the result of (i) by the previous iteration x; (iii) subtracting the result of (ii) from 3; and (iv) multiplying the result of (iii) by half of the previous iteration x. According to another aspect there is provided a calculator unit for determining an initial value for use in a iterative process for calculating an estimate of the reciprocal square root of a number A, the calculator unit comprising circuitry for (a) rounding the number A to the nearest number of the form 2, where J is an integer; (b) if J is odd, rounding J up to the nearest even number to give J'; (c) if J is even, setting J to J&#x2032;; and (d) calculating 2to determine the initial value for the reciprocal square root of A.

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London, United Kingdom

Michael Fitton