International Business Machines Corporation

Kabushiki Kaisha Toshiba

Sony Computer Entertainment Inc.

Michael Fan Wang

Charles Ray Johns

Mack Wayne Riley

Daniel Lawrence Stasiak

Joachim Gerhard Clabes

David William Boerstler

Eskinder Hailu

Stephen Douglas Weitzel

James Allan Kahle

Michael Norman Day

Jeffrey Douglas Brown

Kazuaki Yazawa

Lawrence Joseph Powell, Jr

Shigehiro Asano

Cedric Lichtenau

Thuong Quang Truong

Hiroki Kihara

Alvan Wing Ng

Iwao Takiguchi

Munehiro Yoshida

Nathan Paul Chelstrom

Tetsuji Tamura

Rolf B Hilgendorf

Balaram Sinharoy

Michael Stephen Floyd

Harm Peter Hofstee

Anand Haridass

Howard Hao Chen

Jonathan James DeMent

Toshiyuki Hiroi

Matthias Seul

Rajat Chaudhry

James Scott Neely

Takashi Omizo

David W Shan

Gricell Co

Siddharth Mehta

Yash Kedia

Jie Jenie Gao

Melia F Gordon

A system for determining code ancestry. The system includes: a memory; and a processor communicatively coupled to the memory. The processor is configured to perform a method comprising: receiving a source code file; parsing a plurality of functions out of the source code file; generating fuzzy fingerprints from the plurality of functions; and storing the fuzzy fingerprints in a graph database.

Software code analysis using fuzzy fingerprinting

A data processing system and processor are provided for tracing thermal data via performance monitoring. A performance monitor is set into a tracing mode. Temperatures are sensed by a digital thermal sensor over a time period. The sensed temperatures are stored in a data structure and a trace of the sensed temperatures is graphically displayed.

Tracing thermal data via performance monitoring

A method and apparatus are provided for calibrating digital thermal sensors. A processor chip with a plurality of digital thermal sensors receives an analog voltage. A test circuit coupled to the processor chip receives a clock signal and a register coupled to the test circuit outputs a value on each clock cycle to a digital thermal sensor in the plurality of digital thermal sensors. The digital thermal sensor transitions an output state in response to the value of the register received in the digital thermal sensor equaling a temperature threshold of the digital thermal sensor. The value of the register at the point of transition is used to calibrate the digital thermal sensor. An incrementer increments the value of the register on each clock cycle in response to the value of the register received in the digital thermal sensor failing to equal the temperature threshold of the digital thermal sensor.

Digital thermal sensor test implementation without using main core voltage supply

A computer implemented method, data processing system, and processor are provided for managing a thermal management system. A determination is made as to whether a plurality of digital thermal sensors is faulty or functional. A power savings mode of at least one unit within the integrated circuit associated with the functional digital thermal sensor is monitored in response to at least one of the plurality of digital thermal sensors being functional. A functional digital thermal sensor is disabled in response to the at least one unit being in a power savings mode.

Support of deep power savings mode and partial good in a thermal management system

A method, system, and computer program product are provided for distributing net power accurately. A workload is simulated operating on an integrated circuit. Net switching activity is determined for a set of nets and a set of subnets in the integrated circuit. Net switching data is generated based on the net switching activity. A net power value is calculated for each individual net and each individual subnet using the net switching data and a net capacitance for each individual net or subnet. Each calculated net power value is assigned to one of a set of source devices that drives the individual net or subnet, wherein the net power is distributed accurately. A net power assignment list is generated based on the assigning of each net power value to one of the set of source devices that drives the individual net or subnet.

Distributing integrated circuit net power accurately in power and thermal analysis

A computer implemented method, data processing system, and processor are provided for tracing thermal data via performance monitoring. A performance monitor is set into a tracing mode. Temperatures are sensed by a digital thermal sensor over a time period. The sensed temperatures are stored in a data structure and a trace of the sensed temperatures is graphically displayed.

An apparatus is provided to reduce transient current swings during mode transitions. Traditionally, transient supply voltage fluctuations on a chip account for a large portion of the power supply. The number of series inductances and resistances are typically minimized, while adding large decoupling capacitances between the supply voltage and ground. However, situations may arise where reduction of series inductances and resistances cannot be accomplished. Therefore, to assist in controlling the transient current swings, reduction of clocking frequencies are performed in a controlled manner.

Circuit to reduce transient current swings during mode transitions of high frequency/high power chips

A circuit for transitioning clocking speeds, or frequencies, is provided. With this circuit, a clocking circuit providing a first clock signal at a first clock frequency is coupled to a counter. A comparator and a first divider are coupled to an output of the counter. The first divider outputs a second clock signal at a second clock frequency. A second divider is interposed between the clocking circuit and the counter. A processor is coupled to an output of the first divider.

Circuit to reduce power supply fluctuations in high frequency/high power circuits

A computer implemented method, data processing system, and processor are provided for logging a maximal temperature in an integrated circuit. A digital thermal sensor senses a temperature in the integrated circuit. The sensed temperature of the digital thermal sensor is read and a determination is made as to whether the sensed temperature is higher than a current maximal temperature. The sensed temperature is logged in response to the sensed temperature being higher than the current maximal temperature. The sensed temperature becomes a new maximal temperature for the integrated circuit.

Maximal temperature logging

A computer implemented method, data processing system, and processor are provided for thermal interrupt generation. An interrupt temperature is set to a first temperature and an interrupt direction is to a greater than or equal to determination. A determination is made as to whether a sensed temperature from a digital thermal sensor meets or exceeds the interrupt temperature in response to the interrupt direction. A first interrupt is generated in response to the sensed temperature meeting or exceeding the interrupt temperature.

Thermal interrupt generation

A computer implemented method, data processing system, and processor are provided for implementation of thermal throttling logic. A sensed temperature value is received from a digital thermal sensor representing a current temperature of a unit associated with the digital thermal sensor in the integrated circuit. The sensed temperature is reported as the current temperature in a status register. The unit in the integrated circuit is throttled in response to the current temperature exceeding a first predetermined value.

Implementation of thermal throttling logic

A component of a microprocessor-based data processing system, which includes features for regulating power consumption in snoopable components and has gating off memory coherency properties, is determined to be in a relatively inactive state and is transitioned to a non-snoopable low power mode. Then, when a snoop request occurs, a retry protocol is sent in response to the snoop request. In conjunction with the retry protocol, a signal is sent to bring the component into snoopable mode. When the retry snoop is requested, the component is in full power mode and can properly respond to the snoop request. After the snoop request has been satisfied, the component again enters into a low power mode. Therefore, the component is able to enter into a low power mode in between snoops

Method and apparatus for managing the power consumption of a data processing system

The present invention provides for reducing current spikes in a circuit when changing clocking frequencies. A first frequency is applied to a clock distribution network. A final frequency is selected. The first frequency is applied to a logic element over the clock distribution network. A hold signal is applied to the logic element. The clock rate of the clock distribution network is changed from the first frequency to the final frequency. The hold signal is unapplied to the logic element.

Dynamic frequency scaling sequence for multi-gigahertz microprocessors

A computer implemented method, data processing system, and processor are provided for thermal throttle control with minimal impact to interrupt latency. A setting of an interrupt status bit is monitored. A determination is made as to whether an interrupt associated with the interrupt status bit is an unmasked interrupt in response to the interrupt status bit being set. An existing throttling mode is disabled and the interrupt handled in response to the interrupt being unmasked, where the interrupt latency of the integrated circuit is reduced.

Thermal throttle control with minimal impact to interrupt latency

An apparatus, a method, and a computer program are provided to gate a Phased Locked Loop (PLL). In microprocessors, the clock distribution system can account for a substantial amount of power consumption. Gating the PLLs, however, has been difficult because of the usual requirement for a separate clock for control logic and because the PLL requires timed to reacquire phase/frequency lock. Therefore, lock detection logic can be employed to allow the PLL to reacquire phase/frequency lock. Additionally, signals from external devices and the processor can be employed to gate the PLL and allow the processor to be awakened without a need for a separate clock.

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Austin, TX, United States of America

Michael Fan Wang