Synaptics Corporation

Michael F Wall

Carver A Mead

Timothy P Allen

Janeen D Anderson

John C Platt

Glenn E Gribble

Federico Faggin

A synaptic array according to the present invention comprises a plurality of electrically-adaptable elements. Electrons may be placed onto and removed from a floating node in each electrically adaptable element associated with at least one MOS insulated gate field effect transistor, usually the gate of the transistor, in an analog manner, by application of first and second electrical control signals generated in response to an adapt signal. The inputs to all synaptic elements in a row are connected to a common row input line. Adapt inputs to all synaptic elements in a column are connected together to a common column adapt line. The current supplied to all amplifiers in a column is commonly provided by a sense line. In order to adapt the synaptic elements in the M row by N column matrix of the present invention, the voltages to which a given column n of the matrix is to be adapted are placed onto the input voltage lines, and the synaptic elements in column n are then simultaneously adapted by assertion of an adapt signal on the adapt line for column n. The vectors of input voltages for adapting successive columns may be placed sequentially onto the row input voltage lines and used to adapt the columns of synaptic elements by assertion of the adapt signals on the appropriate column adapt lines until the entire array is electrically adapted. After each synaptic element has been adapted, the current flowing through it will be maximized when the voltage at the input of the synaptic element equals the voltage to which the synaptic element has been adapted. An electrically adaptable winner-take-all circuit has its inputs connected to the column-sense lines of the array.

Electrically adaptable neural network with post-processing circuitry

The present invention is a method and apparatus for performing neighborhood processing operations on an n dimensional processing plane. In a simple, two dimensional, example, an M by N processing plane is successively scanned by rows. The output information from each row is presented on column lines. The analog data resulting from a fixed number of successive scans are temporarily held in a multi-stage analog buffer. A computing array is configured to perform the neighborhood operations or other limited co-operand operations on the shifted data. The computing array examines information from a slice made up of selected numbers of successive rows of the entire array, performs the operations on that portion, and provides a series of output signals representative of the result. The analog buffer is pipelined; information from a new row represents only a single row of new data and the contents of the latch stage containing the oldest information is replaced with this new analog data, causing the information from the transducers of the oldest row to be lost. The operation is then performed on the new slice. This sequence is repeated until all representative slices of the total array have had the neighborhood operations performed on them.

Method and apparatus for performing neighborhood operations on a

A linear voltage-to-current converter (LVCC) circuit includes two transistors, one P-channel and one N-channel. The input voltage is applied to the gates of both transistors. The drains of the two transistors are connected. The source of the p-type transistor is connected to a first voltage rail, and the source of the N-channel is connected to a second voltage rail of lower voltage. The output is the difference between the current through the P-channel transistor and the N-channel transistor. A linear current-to-voltage converter (LCVC) circuit is similar to the LVCC circuit, except that the gates of the transistors are tied to the drains of the transistors. The input current is supplied to the drains, and the output voltage is the voltage of the drains.

Circuits for linear conversion between currents and voltages

An adaptable current mirror includes first and second MOS transistors. The first MOS transistor has its gate connected to its drain. A MOS capacitor structure is connected in series between the gate of the first MOS transistor and the gate of the second MOS transistor. Electrons may be placed onto and removed in an analog manner from a floating node associated with the second MOS transistor, usually the gate of the transistor, by application of first and second electrical control signals. A first electrical control signal controls the injection of electrons onto the floating node from an electron injection structure and the second electrical control signal controls the removal of electrons from the floating node by an electron removal structure. A plurality of adaptable current mirrors communicating with a plurality of current-carrying lines may be employed for indicating the output of the one of the plurality of current-carrying lines through which the most current is flowing.

Adaptable MOS current mirror

An adaptable MOS winner take all circuit includes a plurality of adaptable current mirrors. Each adaptable current mirror includes a floating node onto which and from which electrons may be transported by control signals and electrical semiconductor structures. Electrons may be placed onto and removed from a floating node associated with at least one MOS insulated gate field effect transistor, usually the gate of the transistor, in an analog manner, by application of first and second electrical control signals. A first electrical control signal controls the injection of electrons onto the floating node from an electron injection structure and the second electrical control signal controls the removal of electrons from the floating node by an electron removal structure.

CMOS winner-take all circuit with offset adaptation

Circuits for linear conversion between voltages and currents

An MOS current mirror includes a floating node onto which and from which electrons may be transported by control signals and electrical semiconductor structures in order to adapt the current mirror to supply a desired output current when a particular input calibration current is present.

CMOS current mirror with offset adaptation

Linear, continuous-time, two quadrant multiplier

Electrons may be placed onto and removed from a floating node associated with at least one MOS transistor, usually the gate of the transistor, in an analog manner, by application of first and second electrical control signals. A first electrical control signal controls the injection of electrons onto the floating node from an electron injection structure and the second electrical control signal controls the removal of electrons from the floating node by an electron removal structure. An analog MOS integrated circuit comprises an amplifier circuit having a gain much larger than 1. The inverting input into one stage of this amplifier circuit is a floating node forming the gate of at least one MOS transistor. A first capacitor couples an input of the circuit to this floating node. Electrical semiconductor structures are provided for both linearly adding and removing charge from the floating gate, thus allowing the offset voltage of the amplifier to be adapted. An integrated circuit amplifier having a random input offset voltage is adaptable such that the input offset voltage may be cancelled out. An inverting input node is a floating input node and is coupled to a source of input signal by a first capacitor. A second capacitor is connected between the output of the amplifier and the floating node. An electrical learning means allows the floating node to be charged or discharged to a voltage which effectively cancels the input offset voltage.

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Sunnyvale, CA, United States of America

Michael F Wall