Vanguard International Semiconductor Corporation

Michael F Vincent

Luigi Ternullo, Jr

Michael C Stephens, Jr

Jeffrey Scott Earl

Christopher Ematrudo

A circuit for a DRAM is described which, when in test mode, notifies a tester when the self-refresh operation of a dynamic random access memory (DRAM) reaches various stages of completion. By signaling the tester when, i.e., &frac18;, &frac14;, &frac12;, etc. of the self-refresh cycle is reached, the amount of time needed for verification of the self-refresh oscillator frequency is reduced correspondingly by a factor of 8, 4, 2 etc. The signaling of a partial test time is achieved by adding self-refresh status logic circuits which decode the high order most significant bits of the refresh address counter. The activation of the third most significant bit signals completion of &frac18;th of the self-refresh cycle, the activation of the second most significant bit signals completion of &frac14;th of the self-refresh cycle, the activation of the most significant bit signals completion of &frac12; of the self-refresh cycle, and deactivation of the most significant bit signals completion of the self-refresh cycle.

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Michael F Vincent