Intel Corporation

Technology Inc. 64

Michael F Patti

Nicola J Fedele

Kevin Harney

Allen H Simon

Brian Astle

David L Sprague

John M Keith

Lawrence D Ryan

A video signal processor includes cicuitry which may be conditioned by a mode control signal to operate as a single 16-bit adder or as two eight-bit adders. The circuitry includes two eight-bit adders, each of which has a carry-in input terminal and a carry-out output terminal. The carry-out output terminal of one of the adders is selectively coupled, via an AND gate, to the carry-in input terminal of the other adder. The AND gate is controlled by the mode control signal. In the mode where the circuitry operates as two eight-bit adders, additional circuiry is included to detect output values which may exceed the zero to 255 range of valid values and to saturate these invalid values either at zero or 255.

Dual mode combining circuitry

A video signal processor includes circuitry which may be conditioned by a mode control signal to operate as a single 16-bit adder or as two eight-bit adders. The circuitry includes two eight-bit adders, each of which has a carry-in input terminal and a carry-out output terminal. The carry-out output terminal of one of the adders is selectively coupled, via an AND gate, to the carry-in input terminal of the other adder. The AND gate is controlled by the mode control signal. In the mode where the circuitry operates as two eight-bit adders, additional circuitry is included to detect output values which may exceed the zero to 255 range of valid values and to saturate these invalid values either at zero or 255.

Dual mode adder circuitry with overflow detection and substitution

A parallel-pipeline video signal processing system is disclosed which includes a statistical decoder, an arithmetic and logic unit and a pixel interpolator which operate in parallel under the control of sequencing circuitry to expand a compressed video signal. The video signal may have been developed using a variety of compression techniques including Huffman-type statistical encoding.

Processor for expanding a compressed video signal

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Plainsboro, NJ, United States of America

Michael F Patti