Analog Devices,inc.

Analog Devices Global

Analog Devices International Unlimited Company

Michael F Keaveney

William Hunt

Patrick Walsh

Colin Gerard Lyden

Hyman Shanan

James Breslin

David J McLaurin

Christopher W Angell

Mohamed A Shehata

Michael William O'Brien

Michael G Tuthill

Emil Ivanov Entchev

Dixian Zhao

Patrick Reynaert

Michael W O'BRIEN

Rotary traveling wave oscillator-based (RTWO-based) frequency multipliers are provided herein. In certain embodiments, an RTWO-based frequency multiplier includes an RTWO that generates a plurality of clock signal phases of a first frequency, and an edge combiner that processes the clock signal phases to generate an output clock signal having a second frequency that is a multiple of the first frequency. The edge combiner can be implemented as a logic-based combining circuit that combines the clock signal phases from the RTWO. For example, the edge combiner can include parallel stacks of transistors operating on different clock signal phases, with the stacks selectively activating based on timing of the clock signal phases to generate the output clock signal of multiplied frequency.

RTWO-based frequency multiplier

Rotary traveling wave oscillators (RTWOs) with distributed stubs are provided. In certain embodiments, an RTWO includes segments that are implemented using distributed stubs to mitigate flicker noise upconversion arising from transmission line dispersion. For example, a distance between the distributed stubs can be selected to intentionally generate a phase difference between transmission line modes, thereby cancelling out phase shifts due to transmission line dispersion. In particular, each segment is subdivided into multiple transmission line sections with a maintaining amplifier electrically connected to one of the sections and a tuning capacitor array connected to adjacent transmission line sections.

Rotary traveling wave oscillators with distributed stubs

Aspects of this disclosure relate to active antenna calibration. In some embodiments, a local oscillator signal can be injected into the receive path for misalignment measurement and calibration of the receive path, a transmit signal from a transmit path can be coupled to a receive path, and the transmit path can be calibrated relative to the receive path.

Active antenna calibration

Apparatus and methods for synchronizing phase-locked loops (PLLs) are provided. In certain implementations, a fractional-N synthesizer includes a PLL and a control circuit that controls a division value of the PLL. The control circuit includes an interpolator, a reset phase adjustment calculator, and a synchronization circuit. The interpolator can control a fractional portion of the PLL's division value. The reset phase adjustment calculator can include a counter for counting a number of cycles of the reference clock signal since initialization of the fractional-N synthesizer, and the reset phase adjustment calculator can generate a phase adjustment signal based on the count. The synchronization circuit can synchronize the PLL in response to a synchronization signal, and can correct for a synchronization phase error indicated by the phase adjustment signal.

Apparatus and methods for synchronizing phase-locked loops

Apparatus and methods for frequency lock enhancement of phase-locked loops (PLLs) are provided. In one aspect, a PLL can include a VCO having a tuning voltage input and a frequency tuning circuit configured to set a frequency band setting of the VCO. The frequency tuning circuit can include a voltage monitor configured to compare the voltage level of the tuning voltage input to one or more tuning voltage threshold levels, a control circuit configured to control at least a frequency band setting and a bias current setting of the VCO, and an amplitude detection circuit configured to compare an amplitude of an oscillation signal of the VCO to one or more amplitude threshold levels.

Apparatus and methods for frequency lock enhancement of phase-locked loops

Provided herein are apparatus and methods for a cascode amplifier topology for millimeter-wave power application. The cascode amplifier can use a neutralized common source stage cascoded with a bootstrapped common gate stage to provide an amplifier topology having enhanced performance, gain, stability and reliability. Additionally, a bootstrap capacitor of the common gate stage can be patterned between the source fingers and the drain fingers of a cascode transistor so as to improve device performance. Operating as an RF power amplifier, a single-stage cascode amplifier using the neutralized common source stage with the bootstrapped common gate stage can provide greater than 15 dB of power gain to signals of the E band.

Apparatus and methods for a cascode amplifier topology for millimeter-wave power application

Apparatus and methods for frequency lock enhancement of phase-locked loops (PLLs) are provided. In one aspect, a PLL can include a VCO and a calibration voltage generation circuit that can generate a calibration voltage for controlling a tuning voltage input of the VCO when the VCO is being coarsely tuned. Additionally, the calibration voltage generation circuit can sense a temperature of the PLL, and can control a voltage level of the calibration voltage to provide compensation based on the sensed temperature. The calibration voltage generation circuit can include a bandgap reference circuit configured to generate a zero-to-absolute-temperature (ZTAT) current and a proportional-to-absolute temperature (PTAT) current, and the calibration voltage can be generated based in part on a difference between the PTAT current and the ZTAT current.

Apparatus and methods for phase-locked loops with temperature compensated calibration voltage

As provided herein, in some embodiments, monolithic oscillators with low phase noise, large swing voltages, wide tuning, and high frequency characteristics are obtained by a monolithic integrated circuit having an oscillator core configured to generate a first output signal, and one or more tuning units operatively coupled to the oscillator core. In some embodiments, the oscillator core is a push-push oscillator core having a bipolar junction transistor, and each of the tuning units uses a FET transistor to present a selectable capacitance. In some embodiments, the tuning units have high-voltage and high-frequency capabilities. In some embodiments, the tuning units use MEMS switches to selectively connect capacitances to the oscillator core. In some embodiments, the oscillator core generates a second signal that has twice the frequency of the first frequency.

Monolithic band switched coupled push-push oscillator

A phase locked loop (PLL) based frequency sweep generator and methods for performing a frequency sweep are disclosed. In one implementation, the frequency sweep generator includes a circuit configured to generate a signal having a saw-tooth wave frequency ramp. The saw-tooth wave frequency ramp includes a rising portion and a resetting portion. The resetting portion has a shorter duration than the rising portion and includes a plurality of steps for decrementing the frequency of the signal.

Phase locked loop (PLL) based frequency sweep generator

A fractional-N synthesizer with programmable output phase including a phase locked loop having an output signal whose frequency is a fractional multiple of an input reference signal, the phase locked loop including a frequency divider. A synchronization circuit responsive to the input reference signal for generating synchronization pulses at integer multiples of M periods of the input reference signal. An interpolator is responsive to F and M, where F is the fractional value and M is the modulus, to provide to the frequency divider an output which is a fractional value equal to, on average, the input fraction. A phase adjustment circuit is responsive to the synchronization circuit for varying the phase of the output signal with respect to the input reference signal.

Fractional-N synthesizer and method of programming the output phase

A fractional-N synthesizer system including a plurality of fractional-N synthesizers all updated to simultaneously generate an output frequency from the same reference frequency, a phase locked loop having an output signal whose frequency is a fractional multiple of the input reference frequency; the phase locked loop including a frequency divider, an interpolator responsive to an input fraction to provide to the frequency divider an output which has a fractional value equal to on average, the input fraction; and a timeout circuit responsive to the reference frequency for generating an output a predetermined time after updating to initialize the interpolator in each synthesizer to the same start conditions for locking together the phase of the frequency outputs of all of the synthesizers at the updated frequency.

Fractional-N synthesizer system and method

A chopped charge pump with matching up and down pulses including a first pair of current sources, a second pair of current sources, and a switching circuit for switching on in a first phase one current source of each pair to provide up current pulses, and the other current source of each pair to provide down current pulses, and switching on in a second phase the other current source of each pair to provide up current pulses, and the one current source of each pair to provide down current pulses to offset error in the current response of the pairs of current sources.

Chopped charge pump

A phase detection apparatus is described for use in a phase lock loop (PLL). The apparatus has a first input for a reference signal, a second input for a loop feedback signal and an output for the phase difference signal. Two D-type flips flops are provided, the first being clocked with the reference signal and the second with the loop feedback signal. The output of the second flip-flop is delayed relative to the first flip-flop, thereby effecting minimal overlap, when using the phase detection apparatus in a fractional- N phase lock loop, of the interpolator activity with that of the charge pump.

Phase frequency detector with adjustable offset

A gain compensation technique for a fractional-N phase lock loop includes locking a reference signal with the N divider feedback signal in a phase lock loop including a phase detector, charge pump, loop filter and voltage control oscillator with an N divider in its feedback loop; driving the N divider with a sigma delta modulator including at least one integrator to obtain a predetermined fractional-N feedback signal; and commanding a scaling in phase lock loop gain by a predetermined factor and synchronously inversely scaling by that factor the contents of at least one of the integrators.

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Lisnagry, Ireland

Michael F Keaveney