International Business Machines Corporation

Michael F Fee

Robert J Sonnelitter, Iii

Deanna Postles Dunn Berger

Arthur J O'Neill, Jr

Ekaterina M Ambroladze

Arthur J O'Neill

Christine Comins Jones

Deanna P Berger

Pak-kin Mak

Diana Lynn Orf

Patrick James Meaney

Michael Andrew Blake

Garrett M Drapala

Diane L Orf

Lisa Cranton Heller

Matthias Klein

Jennifer A Navarro

Cedric Lichtenau

Mary Prilotski Kusko

Ute Gaertner

Timothy Carl Bronson

Frank Siegfried Lehnert

Scott Barnett Swaney

Kenneth Douglas Klapproth

Gary E Strait

Ronald J Frishmuth

Christopher J Berry

Craig Raymond Walters

Ralf Winkelmann

Alan P Wagstaff

Jonathan Yang Chen

Deanna Postles Dunn

Carsten Otte

Thomas G Koehler

Hieu Trong Huynh

Edward W Chencinski

Rebecca S Wisniewski

Hanno Eichelberger

Christian Jacobi

Chung-Lung K Shum

Mark S Farrell

Martin Recktenwald

Gregory William Alexander

Adam B Collura

Aaron Tsai

Hans-Werner Tast

Tobias Webel

Gerard M Salem

Barry Watson Krumm

Christian Habermann

Edward James Kaminski, Jr

Ra'ed Mohammad Al-Omari

Christopher Raymond Conklin

Richard Joseph Branciforte

Ashraf ElSharif

Christopher Carney

Walter Niklaus

Taylor J Pritchard

Adolf Martens

Edward T Gerchman

Edward J Kaminski

Arthur J O'Neil, Jr

Anthony P Cullen

To facilitate an efficient processing of contended cache lines, a cache controller that is associated with a requestor receives a fetch request for data from the requestor. The fetch request is associated with a cache scope designation. If the data is in a high-level cache (e.g., L1 cache) associated with the requestor, the cache controller returns the requested data to the requestor. If the data is not in the high-level cache or if the data is not within the cache pool identified by the cache scope of search designation, and/or if obtaining the data is contentious, the controller returns a cache miss, undeliverable data, and request done instruction to the requestor. Such scheme allows or permits address contention events when the requestor deems such events are necessary and/or when important. As such, address contention events, performance, latencies, increased executions times, inefficient use of resources, may be diminished.

Cache management using cache scope designation

The present disclosure relates to a method for a computer system comprising a plurality of processor cores including a first processor core and a second processor core, wherein a data item is exclusively assigned to the first processor core, of the plurality of processor cores, for executing an atomic primitive by the first processor core. The method includes receiving by the first processor core, from the second processor core, a request for accessing the data item, and in response to determining by the first processor core that the executing of the atomic primitive is not completed by the first processor core, returning a rejection message to the second processor core.

Method and processor system for executing a TELT instruction to access a data item during execution of an atomic primitive

Embodiments of the present invention are directed to a computer-implemented method for controller address contention assumption. A non-limiting example computer-implemented method includes a shared controller receiving a fetch request for data from a first requesting agent, the receiving via at least one intermediary controller. The shared controller performs an address compare using a memory address of the data. In response to the memory address matching a memory address stored in the shared controller, the shared controller acknowledges the at least one intermediary controller's fetch request, wherein upon acknowledgement, the at least one intermediary controller resets, wherein the acknowledging comprises exchanging tokens by the shared controller and the at least one intermediary controller, wherein the at least one intermediary controller transmits an identity of the first requesting agent and a type of operation associated with the requested data, and wherein the shared controller transmits an acceptance.

Controller address contention assumption

The present disclosure relates to a method for a computer system comprising a plurality of processor cores, including a first processor core and a second processor core, wherein a cached data item is assigned to a first processor core, of the plurality of processor cores, for exclusively executing an atomic primitive. The method includes receiving, from a second processor core at a cache controller, a request for accessing the data item, and in response to determining that the execution of the atomic primitive is not completed by the first processor core, returning a rejection message to the second processor core.

Executing an atomic primitive in a multi-core processor system

Embodiments of the present invention are directed to a computer-implemented method for controller address contention assumption. A non-limiting example computer-implemented method includes a shared controller receiving a fetch request for data from a first requesting agent, the receiving via at least one intermediary controller. The shared controller performs an address compare using a memory address of the data. In response to the memory address matching a memory address stored in the shared controller, the shared controller acknowledges the at least one intermediary controller's fetch request, wherein upon acknowledgement, the at least one intermediary controller resets. In response to release of the data by a second requesting agent, the shared controller transmits the data to the first requesting agent.

Topology of clusters of processors of a computer configuration, configured to support any of a plurality of cache coherency protocols, is discovered at initialization time to determine which one of the plurality of cache coherency protocols is to be used to handle coherency requests of the configuration.

Configuration based cache coherency protocol selection

Methods and apparatuses for performing a quiesce operation in a multithread environment is provided. A processor receives a first thread quiesce request from a first thread executing on the processor. A processor sends a first processor quiesce request to a system controller to initiate a quiesce operation. A processor performs one or more operations of the first thread based, at least in part, on receiving a response from the system controller.

Quiesce handling in multithreaded environments

In an approach for managing data transfer across a bus shared by processors, a request for a first set of data is received from a first processor. A request for a second set of data is received from a second processor. First portions of the first set of data and the second set of data are written to a buffer. Additional portions of each set of data are written to the buffer as portions are received. It is determined that a portion of the first set of data has a higher priority to the bus than a portion of the second set of data based on a priority scheme, wherein the priority scheme is based on return progress of each respective set of data having at least a portion of data in the buffer. The portion of the first set of data is granted access to the bus.

Multiprocessor cache buffer management

Aspects include techniques for implementing a clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry for encoding and correction of a chip. A computer-implemented method may include initializing a scan of the chip including data and a set of check bits protecting the data; applying a global control bit to a latch on the chip; and applying an additional clock to the latch so the check bits are updated using the on-chip circuitry.

Clock path technique for using on-chip circuitry to generate a correct encode pattern to test the on-chip circuitry

Aspects include techniques for bypassing an encoded latch on a chip during a test-pattern scan and using on-chip circuitry to generate a desired encoded pattern, which is inserted into a scan-bypassed latch, to test the on-chip circuitry for defects. A computer-implemented method may include applying a global control bit to the chip; initializing a scan of the chip while bypassing the encoded latch; and applying an extra scan clock to initiate the encoded latch after completing the scan, wherein the encoded latch is updated with check bits generated by the on-chip circuitry.

Bypassing an encoded latch on a chip during a test-pattern scan

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Cold Springs, NY, United States of America

Michael F Fee