Intel Corporation

Michael F Cole

Robert G Blankenship

Krishnakanth Venkata Sistla

David M Puffer

Ankush Varma

Buck Gremel

Subramaniam M Maiyuran

Bruce A Young

Pattabhiraman K

Ganapati Srinivasa

Vikranth Vemulapalli

Geeyarpuram N Santhanakrishnan

Mark Rowland

Scott A Goble

T Scott Cummins

Alexandr Kurylev

Ankita A Agarwal

Sriharsha Vadlamani

Piotr Reiter

Methods, systems and apparatuses may provide for technology that includes configuration registers to maintain state information, a filter coupled to the configuration registers, the filter to extract transactions of interest from a plurality of incoming transactions based on the state information, wherein the transactions of interest are extracted on a transaction-by-transaction basis, a first hardware path coupled to the filter, the first hardware path to generate a count of the transactions of interest on a cycle-by-cycle basis, a second hardware path coupled to the filter, the second hardware path to measure a total latency of the transactions of interest on the cycle-by-cycle basis, and an output interface coupled to the first hardware path and the second hardware path, the output interface to determine an average latency of the transactions of interest based on the count of the transactions of interest and the total latency of the transactions of interest.

Technology to measure latency in hardware with fine-grained transactional filtration

Systems and methods for minimally intrusive instruction pointer-aware processing resource activity profiling are disclosed. In one embodiment, a graphics processor includes a grouping of processing resources and control logic that is associated with the grouping of processing resources. The control logic is configured to sample a state of at least one processing resource of the grouping of processing resources and to determine activity data from the state with the activity data including at least one of stalls and reason counts for stalling activity, instruction types, pipeline utilization, thread utilization, and shader activity.

Method and apparatus for minimally intrusive instruction pointer-aware processing resource activity profiling

Methods and apparatus relating to low-overhead utilization-aware link-width modulation to reduce power consumption in interconnects are described. In one embodiment, link width modulation logic adjusts the width of an interconnect link. More particularly, the link width modulation logic causes the interconnect link to transition from a first width to a second width based on comparison of a utilization value associated with the interconnect link against at least one of a plurality of utilization threshold values. Other embodiments are also disclosed and claimed.

Utilization-aware low-overhead link-width modulation for power reduction in interconnects

Methods and apparatus relating to low-overhead utilization-aware link-width modulation to reduce power consumption in interconnects are described. In one embodiment, a link width modulation logic adjusts the width of an interconnect link. More particularly, the link width modulation logic causes the interconnect link to transition from a first width to a second width based on comparison of a utilization value associated with the interconnect link against at least one of a plurality of utilization threshold values. Other embodiments are also disclosed and claimed.

A discussion of a dynamic configuration for a prefetcher is proposed. For example, a thread specific latency metric is calculated and provides dynamic feedback to the software on a per thread basis via the configuration and status registers. Likewise, the software can optionally use the information from the registers to dynamically configure the prefetching behavior and allows the software to be able to both query the performance and configure the prefetcher.

Method, apparatus, and a system for dynamically configuring a prefetcher based on a thread specific latency metric

A method and apparatus for performing a mid transaction refresh of DRAM and handling a suspend signal from a master. A timer is used to provide a refresh request at predetermined intervals. The refresh request is made to a DRAM state machine. The DRAM state machine performs a DRAM refresh responsive to the refresh request. The refresh is performed by manipulating the RAS and CAS signal while showing a master of the transaction a series of wait states. The suspend signal from the master is received by a DRAM state machine. The DRAM state machine will loop within its then current state as long as the suspend signal is asserted. The RAS, CAS and other control signals are maintained in the states existing when the suspend signal was asserted unless external signals (e.g., a refresh request) force a change in state of the control signals. At least one CAS state machine handles the assertion of CAS. The CAS state machine is suspended responsive to the suspend signal and will bounce between a suspend state and a predetermined state as long as the suspend signal is asserted. The CAS state machine will be suspended if at all before the falling edge of a write transfer, or before the rising edge of a read transfer.

Memory controller performing a mid transaction refresh and handling a

A memory interface device for interfacing between the local bus and a memory bus. The memory bus is coupled to a static memory and a dynamic memory. The interface device includes first and second internal buses coupled to a selecting device. The selecting device selectively couples one of the first and second internal buses to the memory bus. The memory interface device further includes an interface control unit having an input coupled to the local bus for receiving address and control signals. The interface control unit further has an output, coupled to the first internal bus for generating gating each data transfer in the burst in response to the address and control signals.

Growing community of inventors

El Dorado Hills, CA, United States of America

Michael F Cole