Texas Instruments Corporation

Lsi Logic Corporation

Michael F Chisholm

Andrew T Appel

Manoj K Jain

David W Daniel

David I Forehand

Gayle W Miller

Derryl D Allman

Hong Yang

Yunlong Liu

Darvin R Edwards

Gregory Barton Hotchkiss

Yufei Xiong

Reynaldo M Rincon

Dianne G Pinello

Viswanathan Sundararaman

In described examples, a device includes a semiconductor substrate; a buried layer; and a trench with inner walls extending from the buried layer to a surface of the semiconductor substrate, the trench having sidewalls, a bottom wall, a barrier layer including a titanium (Ti) layer covering the sidewalls and the bottom wall, and a filler including more than one layer of conductor material formed on the barrier layer.

Transistor device with sinker contacts and methods for manufacturing the same

A semiconductor device and process for making the same are disclosed which use reticulated conductors and a width-selective planarizing interlevel dielectric (ILD) deposition process to improve planarity of an interconnect layer. Reticulated conductor is used in place of a solid conductor where the required solid conductor width would be greater than a process and design dependent critcal width (conductors smaller than the critical width may be planarized by an appropriate ILD deposition). The reticulated conductor is preferably formed of integrally-formed conductive segments with widths less than the critical width, such that an ILD formed by a process such as a high density plasma oxide deposition (formed by decomposition of silane in an oxygen-argon atmosphere with a back-sputtering bias) or spin-coating planarizes the larger, reticulated conductor as it would a solid conductor of less than critical width. Using such a technique, subsequent ILD planarization steps by, e.g., chemical mechanic polishing or etchback, may be reduced or avoided entirely.

Enhancement in throughput and planarity during CMP using a dielectric stack containing an HDP oxide

A conductive via pattern ( ) between the uppermost metal interconnect layer (M ) and next underlying metal interconnect layer (M ) in the bond pad areas strengthens the interlevel dielectric (ILD ) between metal layers (M and M ). The conductive via layer ( ) may, for example, comprise parallel rails ( ) or a grid of cross-hatch rails ( ). By spreading the stress concentration laterally, the conductive via layer ( ) inhibits micro-cracking from stress applied to the bond pad ( ).

Approach to structurally reinforcing the mechanical performance of silicon level interconnect layers

A semiconductor device and process for making the same are disclosed which use reticulated conductors and a width-selective planarizing interlevel dielectric (ILD) deposition process to improve planarity of an interconnect layer. Reticulated conductor is used in place of a solid conductor where the required solid conductor width would be greater than a process and design dependent critical width (conductors smaller than the critical width may be planarized by an appropriate ILD deposition). The reticulated conductor is preferably formed of integrally-formed conductive segments with widths less than the critical width, such that an ILD formed by a process such as a high density plasma oxide deposition (formed by decomposition of silane in an oxygen-argon atmosphere with a back-sputtering bias) or spin-coating planarizes the larger, reticulated conductor as it would a solid conductor of less than critical width. Using such a technique, subsequent ILD planarization steps by e.g., chemical mechanic polishing or etchback, may be reduced or avoided entirely.

Conductor reticulation for improved device planarity

A method of fabricating a semiconductor wafer having a polishing endpoint layer which is formed by implanting ions into the wafer includes the step of polishing the wafer in order to remove material from the wafer. The method also includes the step of detecting a first change in friction when material of the ion-implanted polishing endpoint layer begins to be removed during the polishing step. The method further includes the step of detecting a second change in friction when material of the ion-implanted polishing endpoint layer ceases to be removed during the polishing step. Moreover, the method includes the step of terminating the polishing step in response to detection of the second change in friction. An apparatus for polishing a semiconductor wafer down to an ion-implanted polishing endpoint layer in the wafer is also disclosed.

Method and apparatus for detecting an ion-implanted polishing endpoint layer within a semiconductor wafer

Techniques for fabricating integrated circuits having devices with gate oxides having different thicknesses and a high nitrogen content include forming the gate oxides at pressures at least as high as 2.0 atmospheres in an ambient of a nitrogen-containing gas. In one implementation, a substrate includes a first region for forming a first device having a gate oxide of a first thickness and a second region for forming a second device having a gate oxide of a second different thickness. A first oxynitride layer is formed on the first and second regions in an ambient comprising a nitrogen-containing gas at a pressure in a range of about 10 to about 15 atmospheres. A portion of the first oxynitride layer is removed to expose a surface of the substrate on the second region. Subsequently, a second oxynitride is formed over the first and second regions in an ambient comprising a nitrogen-containing gas at a pressure in a range of about 10 to about 15 atmospheres to form the first and second gate oxides. Respective gate electrodes are formed over the first and second gate oxides. The oxynitride gates can have a nitrogen content in a range of about 0.2 to about 2.0 percent which can prevent the diffusion of boron ions from the gate electrodes into the oxynitride gates, thereby improving device characteristics. The oxynitride gates of different thicknesses are suitable for high and low voltage devices on the same integrated circuit.

Fabrication of differential gate oxide thicknesses on a single integrated circuit chip

A method of polishing a first layer of a semiconductor wafer down to a second layer of the semiconductor wafer is disclosed. One step of the method includes heating a back surface of the semiconductor wafer to a first temperature level so as to cause a front surface of the semiconductor wafer to have a second temperature level. Another step of the method includes polishing the semiconductor wafer whereby material of the first layer is removed from the semiconductor wafer. The polishing step causes the second temperature level of the front surface to change at a first rate as the material of the first layer is being removed. The method also includes the step of halting the polishing step in response to the second temperature level of the front surface changing at a second rate that is indicative of the second layer being polished during the polishing step. Polishing systems are also disclosed which detect a polishing endpoint for a semiconductor wafer based upon heat conducted through the semiconductor wafer.

Method and apparatus for detecting a polishing endpoint based upon heat

An apparatus integrating pad conditioning device (44) with a wafer carrier device (24) for chemical-mechanical polishing applications includes an attaching mechanism (45) for associating conditioning device (44) with wafer carrier device (24). Conditioning surface (84) of conditioning device (44) conditions the polishing pad associates with attaching mechanism (45). Carrier device (24) receives and holds wafer (42) so that wafer (42) and conditioning surface (44) contact the polishing pad (42) to simultaneously condition polishing pad (26) and polish wafer (42).

Apparatus integrating pad conditioner with a wafer carrier for

A pad conditioning method and apparatus for chemical-mechanical polishing. A polishing pad (114) is attached to a platen (112) and used to polish a wafer (116). Rotating arm (118) positions the wafer (116) over the pad (114) and applies pressure. During wafer polishing particles build up on the polishing pad (114) reducing its effectiveness. Either during or in between wafer polishing (or both), conditioning head (122) is applied to pad (114) to remove the particles from pad (114) into the slurry (120). Conditioning head (122) comprises a semiconductor substrate (126) that is patterned and etched to form a plurality of geometries (128) having a feature size on the order of polishing pad (114) cell size.

Application of semiconductor IC fabrication techniques to the

A semiconductor device and process for making the same are disclosed which use reticulated conductors and a width-selective planarizing interlevel dielectric (ILD) deposition process to improve planarity of an interconnect layer. Reticulated conductor 52 is used in place of a solid conductor where the required solid conductor width would be greater than a process and design dependent critical width (conductors smaller than the critical width may be planarized by an appropriate ILD deposition). The reticulated conductor is preferably formed of integrally-formed conductive segments with widths less than the critical width, such that an ILD 32 formed by a process such as a high density plasma oxide deposition (formed by decomposition of silane in an oxygen-argon atmosphere with a back-sputtering bias) or spin-coating planarizes the larger, reticulated conductor as it would a solid conductor of less than critical width. Using such a technique, subsequent ILD planarization steps by, e.g., chemical mechanic polishing or etchback, may be reduced or avoided entirely.

A pad conditioning method and apparatus for chemical-mechanical polishing. A polishing pad (114) is attached to a platen (112) and used to polish a wafer (116). Rotating arm (118) positions the wafer (116) over the pad (114) and applies pressure. During wafer polishing particles build up on the polishing pad (114) reducing its effectiveness. Either during or in between wafer polishing (or both), conditioning head (122) is applied to pad (114) to remove the particles from pad (114) into the slurry (120). Conditioning head (122) comprises a semiconductor substrate (126) that is patterned and etched to fore a plurality of geometries (128) having a feature size on the order of polishing pad (114) cell size.

A structure and method for chemical-mechanical polishing of a semiconductor body (100) having topographical steps (102) on a surface thereof. A first film (104) having a first CMP removal rate is deposited over the surface of a semiconductor body (100). A second film (106) having a second CMP removal rate is deposited over the first film (104). The second removal rate is not equal to the first removal rate. CMP is performed on the semiconductor body (100) such that the first film (104) is initially exposed only over the topographical steps (102). CMP continues until the semiconductor body (100) has a planarized surface. Because one of the films (104, 106) has a high removal rate and the other (106,104) has a low removal rate, a CMP process is provided requiring less time and having better process uniformity and process latitude.

Selective CMP of in-situ deposited multilayer films to enhance nonplanar

Semiconductor substrate conditioning head having a plurality of

A compact system and method for chemical-mechanical polishing. A polishing pad (114) is attached to a non-rotating platen (112) and used to polish a wafer (116). Rotating arm (118) positions the wafer (116) over the pad (114) and applies pressure. Energy (e.g. ultrasonic) is coupled from device (122) to the platen (112). Energy is thus applied to the pad/wafer interface to aid in the removal of surface material from wafer (116) and for pad conditioning. New slurry is added to wash the particles off the edges of the pad (114).

Compact system and method for chemical-mechanical polishing utilizing

Only the areas of the CdTe/HgCdTe interface of a FPA detector circuit which is coupled by an epoxy to a silicon-based integrated circuit that require interdiffusing are heated to a sufficiently high temperature or have photons of light impinging thereon for a sufficient time to cause interdiffusion of the two layers by the travel of tellurium into the HgCdTe and the travel of mercury into the CdTe. The vast majority of the wafer is masked with an aluminum thin film to greatly reduce heat gain or photon transmission. An advantage of the process in accordance with the present invention is that only a very small fraction of the HgCdTe/epoxy/silicon-based integrated circuit wafer receives incoming energy during interdiffusion whereby problems caused by the differences in coefficient of thermal expansion between silicon and HgCdTe at the epoxy interface are minimized.

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Plano, TX, United States of America

Michael F Chisholm