Tandy Corporation

Michael F Berger

Sammy D Sawyer

A dual processor system in which one processor is dedicated to input/output tasks while the other is dedicated to high level language tasks when operating as a 16-bit machine. The processors include a first microprocessor which is an 8-bit machine, and a second microprocessor which is a 16-bit machine. The first processor has a memory associated therewith which may, for example, be a 64K memory while the second processor has a larger capacity memory. The second processor does not access the memory of the first processor, however, the first processor can access a portion of the second processor's memory. Access to the second processor's memory is controlled by an arbitrator that is operated by system software to prevent access conflicts. For boot-up during power-up operation, a boot ROM is used, attached to the 8-bit processor having stored therein a boot strap program that is initially loaded into the 8-bit processor memory. If the operating system loaded from a diskette indicates 8-bit software, then the 16-bit processor is maintained reset or halted. On the other hand, if the operating system is a 16-bit system, then the boot program loads the 16-bit memory making the 16-bit processor the main processor. The 8-bit processor then functions as an I/O processor. This boot-up procedure allows the 8-bit processor to turn on first and makes the system initially appear as an 8-bit processor system. In this way the system is compatible with software written for an 8-bit machine even though the system is normally run and identified as a 16-bit machine.

Co-processor combination

Circuitry for automatically configuring the operating system software of a computer is disclosed. The circuitry includes a revision port which generates a unique eight-bit code indicating the latest revision level of the main circuit board in the computer. Each time revisions are made in the board during manufacturing or each time a circuit board containing new revisions is put into the system by maintenance or service personnel, the eight-bit code generated by the port is changed. During the process of configuring the operating system software, the central processing unit reads the code generated by the port and uses the revision information to load and link software routines which will operate properly with the revised circuitry.

Computer revision port

A circuit for generating refresh signals for a dynamic, random access memory is disclosed. The circuit comprises a timer which periodically generates refresh request signals. Each refresh request signal increments a refresh request counter. In normal system operation, after a memory access cycle, a refresh cycle is performed if there is a non-zero count in the counter. At the start of each refresh cycle, the counter is decremented and the refresh address to the memory is changed. Refreshing of the memory continues until the count is zeroed. If, for some reason, memory accesses are not performed within the memory refresh time limit, the count in the counter reaches a critical limit and a non-maskable interrupt is generated to the system processor causing it to access an interrupt vector in the memory and force refresh cycles.

Dynamic memory refresh circuit

A memory management system for providing memory protection for various programs running in a computer such as a 16-bit multi-tasking computer system. The scheme of the present invention provides address translation so as to provide separation of memory spaces. In this connection, each program in the machine has associated therewith, two numbers including an offset number and a limit number. Each program is written so that its base starting address is at the same predetermined address, preferably zero. The address space for each program is separated in memory by adding the offset number for that program to the base address to provide the physical address number. The program is prevented from accessing any memory area outside of its allotted area by comparing the sum of the offset and processor addresses to the limit number. If the result is less than the limit number, the computed address is valid, and if it is outside the limit number then the computed address is considered invalid and an error routine is initiated.

Memory management system

An input/output bus structure for a computer system is disclosed in which the computer's central processor is fully protected from 'foreign' I/O devices in that all of the incoming and outgoing bus signals are buffered and the buffer stores can be disabled under software control. To attach an input/output device on the input/output bus, certain requirements, both hardware and software, must be met. The input/output bus is enabled by writing a predetermined bit pattern to a preselected output port. In response to the bit pattern, hardware in the input/output port enables the input/output bus tranceivers to receive and send information.

Input/output buffer circuitry

Data synchronization apparatus for a 1500 baud computer-audio frequency magnetic tape recorder interface is disclosed. The synchronization apparatus automatically detects bit cell boundaries and synchronizes at both the bit level and the byte level even if the audio waveform as read from the tape is inverted, as is the case with some tape recorders. Synchronization is performed by squaring the audio waveform and measuring two successive time intervals occurring between three successive positive-going transitions and subtracting the resulting measurements. If the calculated difference is less than a predetermined amount, positive-going transitions of the waveform are selected as bit cell boundaries. If, on the other hand, the calculated difference is greater than the predetermined amount, negative-going edges are selected as bit cell boundaries. Synchronization is achieved on a byte level by shifting incoming data into a first-in/first-out buffer and examining the stored data for a predetermined bit pattern.

Growing community of inventors

Fort Worth, TX, United States of America

Michael F Berger