Exten Technologies, Inc.

Ovh US LLC

Michael Enz

Ashwin Kamath

Daniel B Reents

Harish Kumar Shakamuri

Rukhsana Ansari

Jayaram Bhat

Chidambara Rameshkumar

Todd Blackmon

Disaggregated storage clusters are disclosed. These disaggregated storage clusters include a plurality of storage targets coupled to each other through a switch and including storage targets including storage and data services storage targets. Data and requests can for storage areas maintained by the storage cluster can be routed between the target of the storage clusters based on pipeline definitions for those storage areas.

Elastic scaling in a storage network environment

Methods, systems, and apparatuses for a high availability (HA) storage cluster comprising a switch, a set of storage resources, and a set of nodes. Each node includes an HA module. The HA module maintains a real storage object representing a storage resource that provides an interface for accessing the storage resource. The HA module maintains a ghost storage object corresponding to the real storage object. The ghost storage object is configured to return an error in response to a call to the interface when the command is an I/O command and return a valid path when the command is a discovery command, connect command, or namespace ID command. When the node owns the storage resource, the interface of the real storage object is called to execute the command. Otherwise, the interface of the ghost storage object is called to respond to the command.

Adaptive namespaces for multipath redundancy in cluster based computing systems

Embodiments as disclosed herein provide for methods and systems that give firmware in a given node the ability to control the hardware configuration and activity of every endpoint in every remote node within the array. The standard, inter-node, message passing interconnect and protocol are utilized for this purpose.

System and method for sending messages to configure remote virtual endpoints in nodes of a systolic array

A storage target comprising a computer memory configured with storage provisioning parameters and a map of initiator information to the storage provisioning parameters. The storage target is configured to receive a discovery request from a requesting initiator, extract identifying information from the discovery request, determine a set of storage provisioning parameters to which the requesting initiator maps based on the extracted identifying information and the map of initiator information to storage provisioning parameters, dynamically create a new virtual target for the requesting initiator according to the set of storage provisioning parameters, dynamically create a storage partition from storage space of a plurality of storage devices according to the set of storage provisioning parameters, assign the storage partition to the new virtual target and return information about the new virtual target to the requesting initiator to allow the requesting initiator to connect to the new virtual target.

Target optimized auto provisioning of storage in a discoverable storage network

Embodiment of a storage stack are disclosed whereby increased performance and other technical improvements are achieved by an application requesting access (e.g., asynchronously) to an address, returning a buffer, and the application issuing a buffer release when the operation is complete.

Systems and methods for accessing non-volatile memory and write acceleration cache

Systems and methods (including hardware and software) are disclosed for us in a multi-core, multi-socket server with many RDMA network adapters and NVME solid state drives. One of the features of the subject matter is to optimize the total IO throughput of the system by first replacing software locks with non-interruptible event handlers running on specific CPU cores that own individual software data structures and hardware queues, and second by moving work to that CPU affinity without stalling due to software lock overhead.

Lock-free datapath design for efficient parallel processing storage array implementation

Methods and System for use on a memory controller are disclosed which provides atomic compute operations of any size using an asynchronous, pipelined message passing interface between clients and the memory controller.

System memory controller with atomic operations

The present subject disclosure provides a switch architecture with data and control path systolic array that can be used for real time data analysis or Artificial Intelligence (AI) learning. A systolic array is described which analyzes the TLPs received by an uplink port and processes the TLPs according to pre-programmed rules. Then the TLP is forwarded to a destination port. The reverse operation is described as well.

Switch with data and control path systolic array

The present technique presents a hardware mechanism by which high performance computational engines utilize external/system memory buffers for data source and sync thus requiring a minimized amount of local buffering and imposing almost no buffer or data size limitations.

High performance raid operations offload with minimized local buffering

Systems and methods (including hardware and software) are disclosed where all common RAID storage levels are implemented for multi-queue hardware by isolating RAID stripes to a single central processing unit (CPU) core affinity. Fixed CPU affinity is used for any piece of data that may be modified. Instead of blocking CPUs that must access or modify a piece of data, the request is efficiently moved to the CPU that owns that data. In this manner the system is completely asynchronous, efficient, and scalable.

Lock-free raid implementation in multi-queue architecture

The present subject disclosure presents a hardware mechanism and usage model for using a compute element of a systolic array to handle messages from an RQ (Receive Queue) to SQ (Send Queue) without requiring a copy between queues and also minimizing the local processor's interaction with the send and receive queue hardware.

Auto zero copy applied to a compute element within a systolic array

The present subject disclosure provides a PCIe switch architecture with data and control path systolic array that can be used for real time data analysis or Artificial Intelligence (AI) learning. A systolic array is described which analyzes the TLPs received by an uplink port and processes the TLPs according to pre-programmed rules. Then the TLP is forwarded to a destination port. The reverse operation is described as well.

Growing community of inventors

Fargo, ND, United States of America

Michael Enz