International Business Machines Corporation

Michael Edward Wazlowski

Robert Brett Tremaine

Charles Otto Schulz

T Basil Smith, Iii

Peter Anthony Franaszek

Lixin Zhang

Yaoqing Gao

Patrick M Bland

John Timothy Robinson

Thomas Basil Smith, Iii

R Brett Tremaine

Steven Wayne White

Chin-Long Chen

Allan Henry Kielstra

Roch Georges Archambault

Francis Patrick O'Connell

Gheorghe Calin Cascaval

Kenneth Blair Ocheltree

Kwok-Ken Mak

Tu-Chih Tsai

Lorraine Maria Herger

A solution for cooperative data prefetching that enables software control of a memory-side data prefetch and/or a processor-side data prefetch is provided. In one embodiment, the invention provides a solution for generating an application, in which access to application data for the application is improved (e.g., optimized) in program code for the application. In particular, a push request, for performing a memory-side data prefetch of the application data, and a prefetch request, for performing a processor-side data prefetch, are added to the program code. The memory-side data prefetch results in the application data being copied from a first data store to a second data store that is faster than the first data store while the processor-side data prefetch results in the application data being copied from the second data store to a third data store that is faster than the second data store.

Software solution for cooperative memory-side and processor-side data prefetching

The present invention provides a computer implemented method, apparatus, and computer usable program code for compiling instructions to manage a cache system. Loop constructs are analyzed to identify data usage characteristics for cache and prefetching conditions in instructions to form identified prefetch conditions. A set of control instructions are inserted into the instructions based on the data usage characteristics and the identified prefetch conditions to form multiple modified instructions. The set of multiple modified instructions are compiled to generate code for execution to form compiled instructions. The set of control instructions in the compiled instructions form a cache management policy to control movement of data in a memory system during execution of the compiled instructions.

Method and apparatus for software-assisted data cache and prefetch control

A communication system for multiple users whereby an automatic indication of away status is prompted immediately upon a user's departure from the vicinity of a computer or other medium. In a preferred embodiment, this is accomplished, in an instant messaging environment, via a video camera arrangement whereby, upon there being a detection of a user's absence from the immediate vicinity, an automatic prompt is made to indicate away status for the user.

Computer-based communication systems and arrangements associated therewith for indicating user status

A computing system and method employing a processor device for generating real addresses associated with memory locations of a real memory system for reading and writing of data thereto, the system comprising: a plurality of memory blocks in the real memory system for storing data, a physical memory storage for storing the pages of data comprising one or more real memory blocks, each real memory block partitioned into one or more sectors, each comprising contiguous bytes of physical memory; a translation table structure in the physical memory storage having entries for associating a real address with sectors of the physical memory, each translation table entry including one or more pointers for pointing to a corresponding sector in its associated real memory block, the table accessed for storing data in one or more allocated sectors for memory read and write operations initiated by the processor; and, a control device for directly manipulating entries in the translation table structure for performing page operations without actually accessing physical memory data contents. In this system, the actual data of the pages involved in the operation are never accessed by the processor and therefore is never required in the memory cache hierarchy, thus eliminating the cache damage normally associated with these block operations. Further the manipulation of the translation table will involve reading and writing a few bytes to perform the operation as opposed to reading and writing the hundreds or thousands of bytes in the pages being manipulated.

Very high speed page operations in indirect accessed memory systems

An architecture, method and apparatus for a data processing system having memory compression and two common memories forming either a single unified memory, or a dual memory system capable of continuous operation in the presence of a hardware failure or redundant 'duplex' computer maintenance outage, without the cost of duplicating the memory devices. A memory controller employs hardware memory compression to reduce the memory requirement by half, which compensates for the doubling of the memory needed for the redundant storage. The memory controller employs error detection and correction code that is used to detect storage subsystem failure during read accesses. Upon detection of a fault, the hardware automatically reissues the read access to a separate memory bank that is logically identical to the faulty bank. After a memory bank is identified as faulty, the memory controller precludes further read access to the bank, permitting replacement without interruption to the application or operating system software operation.

Low cost and high RAS mirrored memory

A method for selecting a line to replace in an inclusive set-associative cache memory system which is based on a least recently used replacement policy but is enhanced to detect and give special treatment to the reloading of a line that has been recently cast out. A line which has been reloaded after having been recently cast out is assigned a special encoding which temporarily gives priority to the line in the cache so that it will not be selected for replacement in the usual least recently used replacement process. This method of line selection for replacement improves system performance by providing better hit rates in the cache hierarchy levels above, by ensuring that heavily used lines in the levels above are not aged out of the levels below due to lack of use.

Prioritizing and locking removed and subsequently reloaded cache lines

An architecture, method and apparatus for a data processing system having memory compression and two common memories forming either a single unified memory, or a dual memory system capable of continuous operation in the presence of a hardware failure or redundant &ldquo;duplex&rdquo; computer maintenance outage, without the cost of duplicating the memory devices. A memory controller employs hardware memory compression to reduce the memory requirement by half, which compensates for the doubling of the memory needed for the redundant storage. The memory controller employs error detection and correction code that is used to detect storage subsystem failure during read accesses. Upon detection of a fault, the hardware automatically reissues the read access to a separate memory bank that is logically identical to the faulty bank. After a memory bank is identified as faulty, the memory controller precludes further read access to the bank, permitting replacement without interruption to the application or operating system software operation.

A method of detecting double-symbol errors and correcting single-symbol errors in a data stream being transmitted in a computer system, e.g., from a memory array to a memory controller. The method includes decoding the data stream which was encoded using a logic circuit which had, as inputs, the data being sent and two address parity bits derived from the system address of the data. Data retrieved from the wrong address can be detected by this code. The logic circuit is described by a parity-check matrix for this ( ) code comprising 128 data bits, 16 check bits, and 2 address parity bits. Although the symbol width of the code is four bits, the code can also be used effectively in memory systems where the memory chip width is eight bits.

(146,130) error correction code utilizing address information

In a processing system having a main memory wherein information is stored in a compressed format for the purpose of gaining additional storage through compression efficiencies and, wherein information stored within the main memory is indirectly accessible by a processor through a compression and decompression mechanisms, an improved memory architecture that accommodates the necessary compressed information data structures, together with a memory region and mapping method for storing information that bypasses the compression and decompression mechanisms to provide low latency processor access to certain address spaces.

Compressor system memory organization and method for low latency access to uncompressed memory regions

In a processing system having a main memory wherein information is stored in a compressed format for the purpose of gaining additional storage through compression efficiencies and, wherein information stored within the main memory is indirectly accessible by a processor through an uncompressed information cache, an improved memory architecture, apparatus and method for detecting and recovering the main memory space used to store &ldquo;stale&rdquo; information associated with cache lines in the &ldquo;modified&rdquo; state, and returning the storage to an unused pool for use in storing other information. This improves the overall compression rate of the system, thus lessening the likelihood of encountering a &ldquo;memory pressure&rdquo; situation where the system runs low on unused memory.

System and method for recycling stale memory content in compressed memory systems

A method of maintaining cache coherency in a computer system including two or more processors sharing information, the processors coupled by two or more interconnects to a memory such that the processors are not directly coupled to the same is disclosed interconnect is disclosed. The method of maintaining cache coherency includes the steps of: accessing and sharing, by a first processor and a second processor, information from the memory and setting path indicators in directories associated with at least two of the interconnects on a respective first and second access path to the memory, and storing the information in respective associated first and second caches; and writing a new value to the information, by a writing processor sharing the information, the writing step including the steps of: invalidating other copies of the information via the path indicators; acquiring exclusive access to the information by changing the path indicators to an exclusive state; and writing the new value to the information, in response to the acquiring step.

Growing community of inventors

New Fairfield, CT, United States of America

Michael Edward Wazlowski