Compaq Computer Corporation, Inc.

Michael E Tubbs

Charles J Stancil

Jeffrey C Stevens

Jens K Ramsey

A circuit for placing an external or L2 cache memory into low power mode in response to certain special cycles executed by the microprocessor. In particular, the special cycles are the stop grant acknowledge special cycle and the halt special cycle. The microprocessor executes the stop grant acknowledge special cycle in response to a request by the computer system to slow down its clock. This request is asserted by the computer system if the system has been idle for a predetermined period of time. The halt special cycle is generated by the microprocessor when a HALT instruction is executed. The stop grant acknowledge and halt special cycles place the microprocessor into a low power state. Since the microprocessor is in low power mode, the L2 cache memory is also placed into low power mode for further power conservation. The L2 cache memory is implemented either with synchronous or asynchronous static random access memories (SRAMs). To place a synchronous SRAM into low power mode, its address strobe input is asserted while its chip select input is deasserted. For an asynchronous SRAM, deasserting its chip select input causes the SRAM to transition into low power mode.

Computer system that places a cache memory into low power mode in

A processing system includes a cache memory system which receives an address and a memory request from a processor. Simultaneously, information is accessed responsive to the address from a main memory and from a cache memory. During access of the information from the main memory and cache memory, it is determined whether the desired information is stored in the cache memory. If so, the information is output from the cache memory; if not, the information is output from the main memory.

Cache memory system with simultaneous access of cache and main memories

Circuit for placing a cache memory into low power mode in response to

An improved programmable logic device programmed to maximize pin usage, and a method of using such a programmable logic device. The programmable logic device is programmed to use a data pin as an input pin by disabling the output buffer driving that pin. Then, when it is desired to drive the data pin as an output pin, the output buffer is enabled, and the pin is driven by a signal generated by the combinatorial logic on the programmable logic device.

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Montgomery, TX, United States of America

Michael E Tubbs