International Business Machines Corporation

Infineon Technologies Ag

Infineon Technologies North America Corp.

Michael E Scaman

Arnold Halperin

Edward John Yarmchuk

William C Leipold

Daniel Nelson Maynard

Timothy G Dunham

David L DeMaris

Shi Zhong

Arthur R Zingher

Henning Haffner

Daniel Guidotti

Scott Marshall Mansfield

Ioana C Graur

Geng Han

Derren Neylon Dunn

Yuet-Ying Yu

Robert Stephen Olyha, Jr

Donald Merte

Charles J Hendricks

Kamalesh S Desai

Bernell E Argyle

James Patrick Wood

Ramya Viswanathan

Amr Y Abdo

Michael M Crouse

Thomas Picunko

Brian J Wojszynski

Christopher W Cline

Vincent A Arena

Toshiaki Yanagisawa

Oseo Park

A system and method for generating test patterns for a pattern sensitive algorithm. The method comprises the steps extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.

System and method for testing pattern sensitive algorithms for semiconductor design

A method is provided for calibrating a model of a lithographic process that includes defining a parameter space of lithographic model parameters that are expected in an integrated circuit layout. The parameter space is defined according to bin values of a lithographic model parameter that span the range from a predetermined minimum and maximum value of the model parameter. The bin values may be incremented uniformly between the maximum and minimum parameter values, or may be distributed according to a weighting. The lithographic model is calibrated to an initial calibration test pattern. The resulting simulated calibration pattern is evaluated to determine whether the model parameter space is adequately populated. If the parameter space is over or under populated, the calibration pattern is modified until the calibration pattern test values adequately populate the parameter space, so that the final calibrated lithographic process model will more reliably predict images over the full range of image parameters.

Calibration of lithographic process models

A method of training an Optical Proximity Correction (OPC) model comprises symmetrizing a complex design to be a test pattern having orthogonal symmetry. Symmetrizing may comprise establishing a axis of symmetry passing through the design, thereby dividing the design into two portions; deleting one of the two portions; and mirror-imaging the other of the two portions about the axis of symmetry. The design may be centered.

Calibration and verification structures for use in optical proximity correction

A method that purposely relaxes OPC algorithm constraints to allow post OPC mask shapes to elongate along one direction (particularly lowering the 1-dimensional MEEF in this direction with the result of an effectively overall lowered MEEF) to produce a pattern on wafer that is circular to within an acceptable tolerance.

MEEF reduction by elongation of square shapes

A method and apparatus for the non-contact electrical test of both opens and shorts in electronic substrates. Top surface electrical test features are exposed to an ionization source under ambient conditions and the subsequent charge build up is measured as a drain current by probes contacting corresponding bottom surface features. Opens are detected by an absence of a drain current and shorts are detected by turning off the ionization source and re-measuring the bottom surface probes with a varying bias applied to each probe in the array.

Ionization test for electrical verification

A computer program product for generating test patterns for a pattern sensitive algorithm. The program product includes code for extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.

Testing pattern sensitive algorithms for semiconductor design

The present invention is an iterative method or procedure involving a series of optical proximity correction (OPC) process steps for refining an integrated circuit design layout on a wafer during a photolithographic process. The iterative method may be applied as a system and computer program to perform classifying and grouping edge fragments according to directional orientations, selecting an edge fragment or a combination of non-opposing edge fragments, calculating an edge placement error of the selected edge fragment and proximally shifting the edge fragment until a quality limitation is met.

Iterative method for refining integrated circuit layout using compass optical proximity correction (OPC)

A wiring test structure includes a plurality of wiring traces configured in an interleaving spiral pattern. At least one of the plurality of wiring traces configured for open circuit testing therein, and at least a pair of the plurality of wiring traces is configured for short circuit testing therebetween.

Wiring test structures for determining open and short circuits in semiconductor devices

An apparatus and method for reducing noise and resonance detractors connected with and E beam tool. The invention provides a plurality of embodiments. In one embodiment, the E beam tool will be calibrated and the results will be then filtered to counter the effects of the noise afterwards. In an alternate embodiment of the present invention, a filter is applied in the actual feedback of the E beam tool for the writing cycle.

Method and structure for reducing effects of noise and resonance associated with an e-beam lithography tool

An apparatus and method for detection of electromechanical and mechanical errors in an electron beam device is provided. First the existing subfield is divided into a gridlike structure where each grid can be considered a target. Then a plurality of target points are provided on each grid for measuring combined directional variances. The separated horizontal and vertical variances is also measured for each of the target points. This leads to the performance of a significance tests, based on the F statistic which we refer to as F , for horizontal and vertical values of each target points during which F values are also obtained. The F values are then compared for horizontal and vertical values and an error alert provided when there is a sufficiently large disparity between the separated F values. In an alternate embodiment of the present invention, a three dimensional grid is also provided to be used in a similar manner. The severity of the error can also be determined based on the disparity of the values. Lastly we refer to a simple F statistic for testing for flatness of the entire field, based on row and field information and refer to it as F .

Method and structure for detection of electromechanical problems using variance statistics in an E-beam lithography device

As disclosed herein, a system and method are provided for detection and measurement of noise on E beam tools and devices including a spectrum analyzer which looks at the different frequency components of the noise. The deflected electron beam from the tool is calibrated in a coarse and fine mode by scanning the beam over a grid-like calibration target. The position of where the bars are detected is compared to where they actually are, and the deflection can be calibrated so that it matches the grid. This invention can utilize a Fast Fourier Transform (FFT) of the time-ordered data which allows one to see peaks associated with noise.

Method and structure for detection and measurement of electrical and mechanical resonance associated with an E-beam lithography tool

A system and method for locating a circuit defect, such as a short or an incipient open, in an electric circuit in a workpiece, such a Printed Circuit Board (PCB) or MultiChip Module (MCM). The circuit is connected to a device for sensitively measuring any resistance change. A thermal stimulus is applied to various subsets of the surface of the workpiece, the thermal stimulus being temporally modulated, and the resistance change measurement correlated with this modulation. By applying well-designed thermal stimulus subsets, resistance measurements may be logically combined which correspond to the plural thermal stimulus subsets. Further, the search region where the defect may be located may be iteratively refined. By measuring the time delay between the thermal stimulus and corresponding resistance change, the depth of a defect below the surface of the workpiece is further determined. Thus the system and method efficiently and accurately locates a defect in three dimensions, even if the workpiece is large, and the defect is small and underneath the surface.

Thermal modulation system and method for locating a circuit defect

A method of locating in a non-destructive and non-invasive manner power plane-to-power plane shorts or I/O net-to-power plane shorts found in a printed circuit board or a multi-chip-module by way of a magnetic field generating probe is described. Thousands of nets can be simultaneously tested to detect not only the presence of a short but also to accurately pinpoint its position. For high resistance shorts, the probe is provided with a pot core housed inductor located at its tip, and is used at low frequencies to minimize the effect of the capacitive impedance between the power planes. For low resistance shorts, the probe is used at high frequencies, delivering equal but opposite current to each of two matched inductors at the tip of the probe to maximize mutual inductive coupling while minimizing electrostatic capacitive coupling with the board or module. In both cases, the highest current stress is on the probe rather than on the expensive and fragile package under inspection. This allows the test to be both more sensitive to high resistance shorts at low frequencies and is less destructive, thereby being less likely to blow filamentary shorts due to high current stresses through the board or module.

Growing community of inventors

Goshen, NY, United States of America

Michael E Scaman