Intel Corporation

Comptek Federal Systems, Inc.

Michael E Rupp

Ronald D Olsen

Jon C Melnik

Michael P Morford

Ronald G Putzbach

Adam V Magoss

Gregory H Kramer

Larry D Fitzgerald

A programmable frame splitter includes a plurality of programmable routers connected to a communication line. The routers contain logic to specify which bits of a frame of serial data are passed to an output of each of the routers. A control unit is provided having logic to control loading and startup of the routers. A field processing unit is provided to receive a bit-clock-out signal from each of the routers and serial data from the communication line. The field processing unit splits the frame of serial data into component fields and performs processing on the field.

Programmable frame splitter

A method, article of manufacture and system to determine a bit rate of a signal is described.

Method, article of manufacture and system to determine a bit rate of a signal

A digital frame determination method and apparatus are provided which collect a data frame from a digital data stream starting at an initial frame start and a nominal frame frequency, test the data frame for alignment based on a set of rules, determine an adjustment value in accordance with the set of rules when the data frame is not aligned, adjust the frame start in accordance with the adjustment value, and repeat until the data frame is aligned and the alignment is verified.

Digital frame determination method and apparatus

A programmable digital phase lock loop produces an output bit clock signal that is synchronized to the rising edge of a reference input signal. In the absence of the reference input signal the programmable digital phase lock loop free runs creating an output bit clock signal at a programmed frequency. Various parameters of the output bit clock signal are programmable including its period, its offset from the reference input signal and its pulse width. There is provided an adjustment in the bit clock signal in the event that the required period thereof is not an integral multiple of the base clock signal of the programmable digital phase lock loop. The adjustment occurs only in the absence of the input reference signal. When the input reference signal is present its rising edge resynchronizes the output bit clock signal to the required frequency.

Programmable digital phase lock loop

A method and apparatus for monitoring a data bus which transfers digital information and commands between components of a system wherein the bus operates according to a designated protocol and is of the serial, asynchronous type employing Manchester encoding. A bus interface provides communication with the bus for receiving and processing message data from the bus, and a storage interface provides communication with an external mass storage device such as a hard disk and also stores an operational program for the data bus recorder. A processor connected to both interfaces receives information from the storage interface which defines message collection via a configuration file, utilizes the operational program from the storage interface, controls operation of the bus interface including initialization and filtering of the bus message traffic in accordance with the configuration file, and controls transfer of recorded bus message data to the external mass storage device via the storage interface. A user operated control unit selectively connected to the processor commands the starting and stopping of bus reading and also provides visible status indications. A personal computer is utilized to specify the configuration file on the mass storage device, i.e. disk, which defines the messages to collect from the bus, and it is utilized to analyze the data recorded from the bus on the disk. The data bus recorder is particularly advantageous for use with one or more MIL-STD-1553 buses.

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Amherst, NY, United States of America

Michael E Rupp