Hewlett Packard Enterprise Development LP

Michael E Malewicki

Thomas Edward McGee

Michael S Woodacre

Frank R Dropps

Steven J Dean

Eric Carl Fromm

Randal Steven Passint

Derek Steven Schumacher

Kirill Malkin

Michael L Anderson

Randy Passint

Example implementations relate to cache coherency protocols as applied to a memory block range. Exclusive ownership of a range of blocks of memory in a default shared state may be tracked by a directory. The directory may be associated with a first processor of a set of processors. When a request is received from a second processor of the set of processors to read one or more blocks of memory absent from the directory, one or more blocks may be transmitted in the default shared state to the second processor. The blocks absent from the directory may not be tracked in the directory.

Application of a default shared state cache coherency protocol

One embodiment can provide a node controller in a multiprocessor system. The node controller can include a processor interface to interface with a processor, a memory interface to interface with a fabric-attached memory, a node-controller interface to interface with a remote node controller, and a cache-coherence logic to operate in a first mode or a second mode. The cache-coherence logic manages cache coherence for a local memory of the processor coupled to the processor interface when operating in the first mode, and the cache-coherence logic manages cache coherence for the fabric-attached memory coupled to the memory interface when operating in the second mode.

System and method for scalable hardware-coherent memory nodes

In exemplary aspects of cache coherency management, a first request is received and includes an address of a first memory block in a shared memory. The shared memory includes memory blocks of memory devices associated with respective processors. Each of the memory blocks are associated with one of a plurality of memory categories indicating a protocol for managing cache coherency for the respective memory block. A memory category associated with the first memory block is determined and a response to the first request is based on the memory category of the first memory block. The first memory block and a second memory block are included in one of the same memory devices, and the memory category of the first memory block is different than the memory category of the second memory block.

Cache coherency management for multi-category memories

To reduce latency and bandwidth consumption in systems, systems and methods are provided for grouping multiple cache line request messages in a related and speculative manner. That is, multiple cache lines are likely to have the same state and ownership characteristics, and therefore, requests for multiple cache lines can be grouped. Information received in response can be directed to the requesting processor socket, and those speculatively received (not actually requested, but likely to be requested) can be maintained in queue or other memory until a request is received for that information, or until discarded to free up tracking space for new requests.

System and method for efficient cache coherency protocol processing

An apparatus, system, and method of enforcing cache coherency in a multiprocessor shared memory system are disclosed. A request is received from a node controller, to process a cache coherent operation on a memory block in a shared memory. Based on the information included in the request, a determination is made as to whether the request was transmitted from a processor that is remote relative to the memory that includes the memory block referenced in the request. If the request is from a remote processor, a hardware-based cache coherency of the system is disabled, and request is processed according to software-based cache coherency protocols and mechanisms. A coherent read request may be translated to a non-coherent request, such as an immediate read request, which does not trigger tracking or storing state and ownership information of the requested memory block, or trigger communications with processors other than those involved with request. Processing a coherent write request may include transmitting an exclusive read request, which is a request for ownership of the memory block identified in the coherent write request, and transmitting a write acknowledgment to the node controller.

Selective disabling of hardware-based cache coherency and enforcement of software-based cache coherency

Multi-node, multi-socket computer systems and methods provide packet tunneling between processor nodes without going through a node controller link. On receiving a packet, the destination node identifier (NID) is examined, and if it is not same as the source socket, then the packet request address is examined. If it is determined that the packet is not for a remote connected socket, then the packet's destination NID and source socket NID are replaced along with recalculated data protection information. The modified packet is then sent to the destination socket over another processor interconnect path.

Packet tunneling for multi-node, multi-socket systems

A high performance computing (HPC) system has an architecture that separates data paths used by compute nodes exchanging computational data from the data paths used by compute nodes to obtain computational work units and save completed computations. The system enables an improved method of saving checkpoint data, and an improved method of using an analysis of the saved data to assign particular computational work units to particular compute nodes. The system includes a compute fabric and compute nodes that cooperatively perform a computation by mutual communication using the compute fabric. The system also includes a local data fabric that is coupled to the compute nodes, a memory, and a data node. The data node is configured to retrieve data for the computation from an external bulk data storage, and to store its work units in the memory for access by the compute nodes.

Workload management system and process

A high-performance computing system, method, and storage medium manage accesses to multiple memory modules of a computing node, the modules having different access latencies. The node allocates its resources into pools according to pre-determined memory access criteria. When another computing node requests a memory access, the node determines whether the request satisfies any of the criteria. If so, the associated pool of resources is selected for servicing the request; if not, a default pool is selected. The node then services the request if the pool of resources is sufficient. Otherwise, various error handling processes are performed. Each memory access criterion may relate to a memory address range assigned to a memory module, a type of request, a relationship between the nodes, a configuration of the requesting node, or a combination of these.

Growing community of inventors

Eau Claire, WI, United States of America

Michael E Malewicki