Micron Technology Incorporated

Michael E Koltonski

Gurtej S Sandhu

Byeung Chul Kim

Matthew S Thorum

Cornel Bozdog

Abhilasha Bhardwaj

John David Hopkins

Chris M Carlson

Shyam Surthi

Richard J Hill

Matthew J King

David A Kewley

Chandra S Tiwari

Yi Hu

Shane J Trapp

Tom Jibu John

Damir Fazil

Xiaosong Zhang

Francois H Fabreguette

Matthew Holland

Deep Panjwani

A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures. Memory cells vertically extend through the stack structure, and comprise a channel material vertically extending through the stack structure. An additional stack structure vertically overlies the stack structure and comprises additional conductive structures and additional insulative structures. First pillar structures extend through the additional stack structure and vertically overlie a portion of the memory cells. Second pillar structures are adjacent to the first pillar structures and extend through the additional stack structure and vertically overlie another portion of the memory cells. Slot structures are laterally adjacent to the first pillar structures and to the second pillar structures and extend through at least a portion of the additional stack structure. A distance between the first pillar structures and the slot structures is substantially equal to a distance between the second pillar structures and the slot structures.

Microelectronic devices including slot structures, and related electronic systems and methods of forming the microelectronic devices

A memory array comprises strings of memory cells. The memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers above a conductor tier. Channel-material-string constructions of memory cells extend through the insulative tiers and the conductive tiers. The channel material of the channel-material-string constructions is directly electrically coupled to conductor material of the conductor tier. Substructure material is in the conductor tier and spans laterally-across and laterally-between bottoms of multiple of the channel-material-string constructions. The substructure material is of different composition from an upper portion of the conductor material. The substructure material comprises laterally-opposing sides that taper laterally-inward moving deeper into the conductor tier. Other embodiments, including method, are disclosed.

Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells

A system for fabricating a semiconductor device structure includes a tool comprising a chamber and a platform within the chamber configured to receive a semiconductor device structure thereon. The tool further includes a heating and cooling system in operable communication with the platform and configured to control a temperature of the platform. The heating and cooling system comprises a cooling system including a cold tank for containing a cold thermal transfer fluid, the cold tank configured to be in fluid communication with the platform, thermal transfer fluid supply piping, and thermal transfer fluid return piping, a heating system including a hot tank for containing a hot thermal transfer fluid having a higher temperature than the cold thermal transfer fluid, the hot tank configured to be in fluid communication with the platform, the thermal transfer fluid supply piping, and the thermal transfer fluid return piping, and at least one temporary storage tank configured to receive at least some of the cold thermal transfer fluid or the hot thermal transfer fluid from at least the thermal transfer fluid return piping after switching a thermal load from the platform from one of the cooling system or the heating system to the other of the cooling system or the heating system. Related methods and tools are disclosed.

Systems for processing one or more semiconductor devices, and related methods

An electronic device comprising a cell region comprising stacks of alternating dielectric materials and conductive materials. A pillar region is adjacent to the cell region and comprises storage node segments adjacent to adjoining oxide materials and adjacent to a tunnel region. The storage node segments are separated by a vertical portion of the tunnel region. A high-k dielectric material is adjacent to the conductive materials of the cell region and to the adjoining oxide materials of the pillar region. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.

Electronic devices comprising adjoining oxide materials and related systems

Tools and systems for processing one or more semiconductor devices, and related methods

Integrated circuitry comprising an array comprises a plurality of conductive vias. Individual of the vias comprise an upper horizontal perimeter comprising opposing end portions. One of the opposing end portions comprises opposing straight sidewalls. The other of the opposing end portions comprises opposing curved sidewalls that join with the opposing straight sidewalls of the one opposing end portion. Other embodiments, including methods, are disclosed.

Integrated circuitry comprising an array, method of forming an array, method of forming DRAM circuitry, and method used in the fabrication of integrated circuitry

Growing community of inventors

Boise, ID, United States of America

Michael E Koltonski