Netlogic Microsystems, Inc

Other

Michael E Ichiriu

Varadarajan Srinivasan

Martin Fabry

Larry A Wall

Sanjay Sreenath

Sandeep Khanna

Ajit Ninan

Bindiganavale S Nataraj

Lan Lee

Masaru Shinohara

Yuefei Ge

A search engine configured to determine whether an input string including a plurality of input characters matches a regular expression including an inexact pattern including a specified range of instances of pattern characters each belonging to a specified set of characters, the search engine including a microcontroller having an input to receive a microprogram embodying the inexact pattern, a first co-processor coupled to the microcontroller and dedicated to determine whether each input character in a first portion of the input string is a member of the specified set of characters, and a second co-processor coupled to the microcontroller and dedicated to determine whether the number of input characters in the first portion of the input string falls within the specified range.

Search engine having multiple co-processors for performing inexact pattern search operations

A network system includes a content search system for determining whether an input string matches a regular expression comprising an exact pattern and an inexact pattern, the content search system including a first search circuit dedicated to perform an exact string match operation to determine whether the input string contains a first portion that matches the exact pattern, and a second search circuit dedicated to perform an inexact string match operation to determine whether the input string contains a second portion that matches the inexact pattern.

Regular expression searching of packet contents using dedicated search circuits

A content search circuit for determining whether an input string matches one or more of a plurality of regular expressions, the content search circuit including an instruction memory for storing a plurality of microprograms, each microprogram embodying a corresponding one of the regular expressions, a control circuit having an input to receive the input string, and having a number of outputs, and a plurality of search engines, each having a first input coupled to a corresponding output of the control circuit and having a second input coupled to the instruction memory, wherein each search engine is selectable to execute any of the microprograms stored in the instruction memory to search the input string for any of the regular expressions embodied in the microprograms.

Search circuit having individually selectable search engines

A content addressable memory (CAM) device including a CAM array, encoding circuit, address circuit and error checking circuit. The encoding circuit generates an address value that corresponds to one of a plurality of match lines included within the CAM array. The address circuit receives the address value from the encoding circuit and enables a data word to be output from a CAM array storage location indicated by the address value. The error checking circuit receives the data word output from the storage location and determines whether the data word contains an error.

Content addressable memory with error signaling

A method of operation within a content addressable memory (CAM) device. An input data word having a plurality of data bits and a plurality of mask bits is received in the CAM device. An encoded data word is generated based, at least in part, on states of the mask bits within the input data word. A write data word is selected from a group of data words that includes at least the input data word and the encoded data word. The write data word is stored within a row of CAM cells within the CAM device.

Content addressable memory device with source-selecting data translator

A content addressable memory (CAM) device having circuitry to generate a biased sequence of addresses. A first counter circuit increments an address value in response to a clock signal and resets the address value to a start address in response to a control signal. A second counter increments a limit value in response to a control signal. A compare circuit compares the address value and the limit value and, if the address value and the limit value have a predetermined relationship, asserts the control signal.

Content addressable memory with priority-biased error detection sequencing

A content addressable memory (CAM) device having a simultaneous write and compare function. The CAM device includes a plurality of rows of CAM cells, and match lines and word lines coupled to the rows of CAM cells. The CAM device further includes a plurality of switching circuits coupled to the word lines and the match lines, each switching circuit being adapted to selectively disable assertion of a match signal on a corresponding one of the match lines based, at least in part, on the state of a corresponding one of the word lines.

Content addressable memory with simultaneous write and compare function

A content addressable memory (CAM) device having an error correction function. The CAM device includes an array of CAM cells, row parity storage elements and column parity storage elements. The row parity storage elements store row parity values that correspond to contents of respective rows of the CAM cells, and the column parity storage elements store column parity values that correspond to respective columns of the CAM cells. A bit error in the array is detected through row and column parity checking that uniquely identifies the row and column location of the error and enables correction of the error.

Error-correcting content addressable memory

A content addressable memory device having an array of multi-compare CAM cells. First and second compare operations are simultaneously performed in the array of multi-compare CAM cells to generate first and second sets of match signals. The first set of match signals is logically combined with the second set of match signals to generate a set of resultant match signals.

Content addressable memory with multi-ported compare and word length selection

A content addressable memory (CAM) has a main array including a plurality of rows of CAM cells, one or more spare rows of CAM cells selectable to functionally replace defective rows of CAM cells in the main array, and a control circuit for disabling the defective rows by writing predetermined data to the defective rows of CAM cells.

Row redundancy in a content addressable memory device

A content addressable memory (CAM) device having a data CAM array and an error CAM array. The data CAM array is provided to store data words, compare the data words with a comparand value, and, if one of the data words matches the comparand value, assert a match signal that corresponds to the matching data word. A priority encoder responds to the match signal by outputting a match address that corresponds to the matching data word. The error CAM array is provided to store at least one error address value and is coupled to the priority encoder to receive the match address. The error CAM array compares the match address with the error address value and asserts a match error signal if the match address matches the error address value.

Content addressable memory with error detection signaling

An inter-row configurable content addressable memory (CAM) system. For one embodiment, the CAM system includes an array of CAM cells having a plurality of rows of CAM cells for storing a data word chain, wherein the data word chain comprises a sequence of at least two data words each stored in a different row of CAM cells, and wherein each row of CAM cells includes a first group of CAM cells for storing a pointer and a second group of CAM cells for storing one of the data words. The pointer of the first data word of the data word chain may be a predetermined number greater than the number of rows in the CAM array. The pointers associated with the other data words of the data word chain each store an address of the previous data word in the data word chain. The CAM system further includes a write circuit for writing the data words into the rows of CAM cells, an address decoder coupled to the CAM array, and a priority encoder coupled to the CAM array.

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Sunnyvale, CA, United States of America

Michael E Ichiriu