Xilinx, Inc.

Barefoot Networks, Inc.

Michael E Attig

Gordon John Brebner

Patrick W Bosshart

Jay Evan Scott Peterson

Michael Gregory Ferrara

Chaitanya Kodeboyina

Steven Licking

John Cruz

Philip Bryn James-Roxby

Ravindra Sunkad

A method of identifying a failed egress path of a hardware forwarding element. The method detects an egress link failure in a data plane of the forwarding element. The method generates a link failure signal in the data plane identifying the failed egress link. The method generates a packet that includes the identification of the egress link based on the link failure signal. The method sets the status of the egress link to failed in the data plane based on the identification of the egress link in the generated packet.

Identifying and marking failed egress links in data plane

Some embodiments provide a network forwarding IC with packet processing pipelines, at least one of which includes a parser, a set of match-action stages, and a deparser. The parser is configured to receive a packet and generate a PHV including a first number of data containers storing data for the packet. A first match-action stage is configured to receive the PHV from the parser and expand the PHV to a second, larger number of data containers storing data for the packet. Each of a set of intermediate match-action stage is configured to receive the expanded PHV from a previous stage and provide the expanded PHV to a subsequent stage. A final match-action stage is configured to receive the expanded PHV and reduce the PHV to the first number of data containers. The deparser is configured to receive the reduced PHV from the final match-action stage and reconstruct the packet.

Expansion of packet data within processing pipeline

A method of configuring a forwarding element that includes several data plane message processing stages. The method stores a set of action codes in an instruction memory in the data plane of the forwarding element. Each action code identifies an operation to perform on a field of a message received at the data plane. The method determines action codes required to process each field of the message in each message processing stage. The method configures a data-plane processing unit of the forwarding element to concurrently perform a group of the action codes in the same data plane processing stage when (i) the action codes are the same and (ii) operate on the same field of the message.

Compiler and hardware interactions to remove action dependencies in the data plane of a network forwarding element

Some embodiments provide a method for a match-action stage of a packet processing pipeline. The method receives a set of data containers storing input packet data values for a particular packet. The set of data containers includes multiple subsets of data containers. The method performs a set of match operations using a first subset of the set of data containers. The method uses a set of arithmetic logic units (ALUs) to generate output packet data values to store in a second subset of the set of data containers. Output packet data values for a third subset of the data containers are generated without the set of ALUs.

Multiple packet data container types for a processing pipeline

A method of configuring a forwarding element that includes several message processing stages. The method identifies a first processing stage that starts processing a first header field of a message and a second processing stage that is the last message processing stage that processes the first header field. The method configures a field of a packet header container to store the first header field from the beginning of the first message processing stage. The method identifies a second header field used in a third processing stage after the second processing stage. The method configures a set of circuitries in the data plane to initialize the container field after the end of the second processing stage. The method configures the field of the container to store the second header field of the message after the end of the second processing stage and before the start of the third processing stage.

Compiler and hardware interactions to reuse register fields in the data plane of a network forwarding element

A method of sharing unit memories between two match tables in a data plane packet processing pipeline of a physical forwarding element is provided. The method, from a plurality of available unit memories of the packet processing pipeline, allocates a first set of unit memories to the first match table and a second set of unit memories to the second match table. The method determines that the first set of unit memories is filled to a threshold capacity after storing a plurality of entries in the first set of unit memories. The method de-allocates a first unit memory from the second match table by moving contents of the first unit memory to a second unit memory in the second set of unit memories. The method allocates the first unit memory to the first match table.

Runtime sharing of unit memories between match tables in a network forwarding element

In one approach for processing a data packet, in at least one stage of a plurality of stages of a pipeline circuit, a respective packet field value is extracted from the data packet. In each stage of the plurality of stages, a respective tuple field value is inserted into a respective tuple register of the stage at a respective offset. The respective tuple field value in the at least one stage is based on the respective packet field value. In each stage of the plurality of stages except a last one of the stages, the contents of the respective tuple register of the stage are provided as input to a next one of the stages.

Tuple construction from data packets

Approaches for selecting a field of data from a packet of data in an n-bit data path. A first selector circuit has m inputs and an output. The m inputs receive respective overlapping subsets of bits of the data path. The first selector selects one of the subsets of bits. Each stage of two or more shift-and-select stages includes a respective second selector circuit having up to m inputs. One of the inputs of the respective second selector circuit inputs an un-shifted version of the subset of bits, one or more others of the up to m inputs of the respective second selector circuit input different shifted versions of the subset of bits, and the respective second selector circuit outputs a selected one of the un-shifted or shifted versions of the subset of bits. The last shift-and-select stage outputs the field of data aligned to the least significant bit.

Circuit and method for extracting fields from packets

A packet processor includes a memory and a programmable compute pipeline. The memory stores microcode that specifies respective sets for the packet types, and the respective set for each type specifies packet fields. The programmable compute pipeline includes a sequence of stages beginning with an initial stage. The initial stage includes an operand selector that extracts a data vector from each packet. The operand selector is programmable to extract the data vector that includes each field specified in the respective set for the type of each packet. Each stage except the initial stage inputs a first version of the data vector and each stage outputs a second version of the data vector. Each stage except the initial stage generates the second version of the data vector that replaces a part of the first version of the data vector with a result that the stage computes from the part.

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San Jose, CA, United States of America

Michael E Attig