Ciena Corporation

Nortel Networks Corporation

Michael Dziawa

Daniel Rivaud

Michael Alain Gazier

Michael John Wingrove

Robert McLaren Thomas

Scott McClennon

Ian Dublin

Francois Tremblay

Michaël Gazier

Carl William Anderson

S Donald McGinn

The present disclosure relates to Ethernet synchronization systems and methods that combines Synchronous Ethernet (Sync-E) and Precision Time Protocol (PTP) IEEE 1588 algorithms. The present invention includes systems and methods for Ethernet networks and node configurations that include a set of rules on node placement, such as Boundary Clock (BC) nodes and Sync-E nodes, a clock selection algorithm, a holdover algorithm, and the like. Advantageously, the present invention provides an architecture that allows practical and real-world useful clock propagation through placement of BCs and Sync-E nodes for best performance. Practical experience and theoretical design are embodied in the present invention to define a very specific set of rules on how to build a network capable of providing accurate and reliable synchronization. The present invention includes clock selection that unifies Sync-E and 1588 algorithms.

Ethernet network synchronization systems and methods

A system and method for canceling interference over a group of signals. One or more wires in a group of wires are designated to carry one or more reference signals. The one or more reference signals are used to cancel interference from the data carrying signals in the group of signals. Preferably, the one or more reference signals are subtracted from the data carrying signals to cancel interference from the data carrying signals. Analog or digital elements can be used to subtract the one or more reference signals from the data carrying signals. For example, an operation amplifier or a DSP may be used to perform the subtraction. Filters may be used to further adapt the one or more reference signals prior to the subtracting step to optimize interference cancellation. The filters may be either digital or analog.

Method and apparatus to cancel interference over a group of signals

A combined wide area network (WAN) port/synchronization unit that receives inputs including data and timing information and that synchronizes the data for transmission. The unit includes the following components. A network interface receives the input and removes data and primary timing information from the input. A data-path function processes the data. A reference selection unit receives timing information from the network interface as well as timing information from a secondary combined WAN port/synchronization unit. A synchronization control unit selects the most reliable timing information from the plurality of timing information inputs to the reference selection unit. A multiplexor multiplexes the timing information with the processed data across a link.

Network synchronization architecture for a Broadband Loop Carrier (BLC) system

Combined plain old telephone system (POTS) and digital subscriber loop (DSL) line card capable of suppressing low frequency transients. The line card includes the following elements. A DSL receive path receives DSL data from a loop. A POTS receive path receives POTS data from the loop. A combined POTS and DSL transmit path transmits POTS and DSL data to the loop. An impedance generator is coupled between the POTS receive path and the combined POTS and DSL transmit path for synthesizing impedance for signals in the combined POTS and DSL transmit path. A low frequency detector selectively applies a high pass filter to an output of the impedance generator for filtering the low frequency transients. Further, a clipped signal detector and a variable pole high pass filter are provided in the POTS receive path. The clipped signal detector in the POTS receive path triggers a switch that discharges stored transient energy in the receive path. The variable pole high pass filter in the POTS receive path is modified during ringing and hook switch activity, by the line card controller, in order to attenuate transient signals.

Method and apparatus for transient suppression in an integrated POTS/DSL line card

A method and apparatus for interference cancellation in a high-speed modem that includes a first coupler for receiving a differential signal including a received data signal, a second coupler for deriving a common mode signal for the transmitted signal, and a phase-shift circuit coupled to the second coupler for deriving orthogonal signals from the common mode signal. First and second multipliers mix the orthogonal signals with the received signal. First, second, and third integrators integrate the mixed orthogonal signals and the common mode signal to produce orthogonal signal level measurements ITONE and QTONE and a common mode signal level measurement CMTONE, respectively. A controller derives orthogonal correction signals from measurements by dividing ITONE and QTONE respectively by CMTONE and multiplying by an appropriate constant. This output is then used to increment or decrement the signals to the respective digital to analog converters, DACI and DACQ. Multipliers combine these orthogonal correction signals to the orthogonal signals. An adder the combines the corrected orthogonal signals with the received signal for deriving the received data signal by cancelling interference therein.

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Richmond, CA, United States of America

Michael Dziawa