Texas Instruments Corporation

Michael Duc Ho

Duy-Loan T Le

Scott E Smith

A circuit (,) that drives word lines and tests a word line (,) in a semiconductor device is disclosed. A charge circuit (,) couples a supply voltage (VPP) to a charge node (,) according to a potential at a boot node (,). The charge node (,) supplies a charge voltage for the word line (,). In a standard cycle, the boot node (,) is charged to a high voltage, and maintained at the high potential, to keep the word line (,) charged. In a test cycle, the boot node (,) is charged to a high voltage, and then discharged to a low voltage, thereby isolating the charge node (,) and the word line (,). In the event the word line (,) suffers from current leakage, a drop in potential will be detected at the charge rode (,).

Circuit for driving conductive line and testing conductive line for current leakage

A memory circuit is designed with a memory array (113, 115, 117, 119) having a plurality of banks. Each bank is addressable in response to a bank address signal (102), and each bank arranged in rows and columns of memory cells. Each of plural data leads (122) corresponds to a bank. Each data lead is selectively connected to a column of memory cells by a respective select transistor. A first decode circuit (501) has at least one input and one output terminal. The output terminal (525) is coupled to a control gate of at least one of the select transistors. Each of a plurality of second decode circuits (231) corresponds to a respective bank. Each second decode circuit has a memory element (423, 425, 428)), a plurality of input terminals and at least one output terminal. One second decode circuit input terminal (227) is coupled to receive a first address signal. Another second decode circuit input terminal (229) is coupled to receive the bank address signal. The second decode circuit output terminal coupled to the input terminal of the first decode circuit. The second decode circuit is arranged to store the first address signal in the memory element in response to the bank address signal.

Low-power column decode circuit

An integrated circuit memory device (10) includes a large on-chip capacitor (12) that has a high voltage plate and a low voltage plate. The large on-chip capacitor (12) stores charge for a positive voltage supply (VPP) for the integrated circuit memory device (10). The high voltage plate of the large on-chip capacitor (12) is connected to a node (NODE 1) for distributing charge from the large on-chip capacitor. A load (16) is connected to the node (NODE 1) and consumes charge from the high voltage plate to power operations of the integrated circuit memory device (10). The load (16) includes a memory array comprising a plurality of memory cells. The low voltage plate of the large on-chip capacitor (12) is connected to a capacitive voltage reference which has high capacitance and has a voltage-level greater than ground potential and less than the positive voltage supply. In one embodiment, the large on-chip capacitor is a storage/filter capacitor (12) for a boosted high voltage supply (VPP), and the capacitive voltage reference is a memory cell reference voltage (VPLT) which is also connected to a reference plate of memory cell capacitors (28) of the memory cells (20) in the memory array.

Integrated circuit memory device having reduced stress across large

A dynamic random access memory part 30 provides a write per bit feature by locating the respective write mask information latches 118 adjacent the respective local I/O buffers 116. The write mask information thus passes through the data latch 108 and across the data path to the local I/O buffer 116 before being latched. This reduces the area otherwise needed for the additional write mask lead, which in a x8, x16, x32 or x64 bit part can be intolerably large.

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Houston, TX, United States of America

Michael Duc Ho