Texas Instruments Corporation

Michael Douglas Snedeker

Hugo Cheung

Masahiro Yoshioka

Ronald F Cormier

Keith Brouse

A device includes an interface. The interface includes a plurality of pins. The interface further includes first components configured to interpret signals received at the plurality of pins according to a first protocol. The device further includes second components configured to the interpret signals received at the plurality of pins according to a second protocol. The first components are configured to disable the second components in response to a determination that the signals received at the pins correspond to the first protocol. Further, the second components are configured to disable the first components in response to a determination that the signals received at the pins correspond to the second protocol.

Protocol auto-detection

A current loop includes a receiver assembly and a transmitter assembly. The current loop also includes: a first conductor between the receiver assembly and the transmitter assembly; and a second conductor between the receiver assembly and the transmitter assembly to complete the current loop. The transmitter assembly includes: a Highway Addressable Remote Transducer (HART) modem; a component in communication with the HART modem via a partial set of Universal Asynchronous Receiver-Transmitter (UART) communication lines; and a break extension protocol controller coupled to or included with the HART modem and configured to support UART and non-UART communications between the HART modem and the component using the partial set of UART communication lines.

Hart-enabled device with reduced communication lines and break extension protocol

A communication system includes a first system input adapted to be coupled to a DC transient current transitioning between a starting level and a target level on a pseudo-sinusoidal path and incudes a second system input adapted to be coupled to a HART signal. The system includes an adder circuit having an output, a first adder input coupled to the first system input and a second adder input coupled to the second system input. The adder circuit provides a superimposed signal comprising the HART signal and the DC transient current.

Pseudo-sinusoidal waveform generator for HART communication

An example apparatus includes: an input adapted to receive a signal modulated with data, counter circuitry coupled to the input and operable to determine a first count value in response to a first period between a first rising edge of the signal and a second rising edge of the signal, the first rising edge indicative of a start bit of the data, and determine a second count value based on a second period between a first falling edge of the signal and a second falling edge of the signal, data capture clock circuitry coupled to the counter circuitry and operable to generate a data capture clock based on the first count value in response to the second count value satisfying a threshold, and demodulator circuitry coupled to the counter circuitry and the data capture clock circuitry, the demodulator circuitry operable to generate a demodulated signal based on the data capture clock.

Phase prediction demodulator circuits and related method

A digital demodulator for use with a Highway Addressable Remote Transducer (HART) modem is provided. Analog input signals are digitized according to a sampling clock rate to produce a discrete time signal. Filtering and edge detection allow determinations of 'mark' or 'space' data in a demodulated signal in conjunction with analyzing a detected signal period, a cycle period, count histories and/or an on/off signal period.

HART FSK digital demodulator

In a carrier detector, the simple latch is replaced with a pulse timer and reference control module which outputs logic high (H) when more than two consecutive toggled signals come within 1.5 baud periods and keeps logic high (H) until it misses a toggled signal for two baud periods. This carrier detector has a tolerance for a false detection which happens when the frequency shifts from lower to higher and the input amplitude level does not reach a detectable level. With this transition, the amplitude level at filter output becomes higher due to the transient response of the filter and eventually this would trigger the comparator for only one baud period. The deglitch circuit, however, ignores this clock edge in the carrier detector as provided herein.

Small and seamless carrier detector

Apparatus and methods process a set of calibration sample values acquired in response to a sequence of calibration touch events generated at known X-Y coordinate positions along a linear path across a touch panel surface. The set of calibration sample values is then curve-fitted to the path to create a characteristic model of the touch panel or a portion thereof. Run-time signals are acquired from X-Y nodes across the panel at the time of a touch event. One or more run-time signal values may be substituted into the panel characteristic model to determine a distance between an X-Y node most strongly associated with the run-time touch event and a point-of-projection of the touch event location onto the path.

Touch panel apparatus and methods

A capacitance measuring system includes analog-digital circuitry () coupled to row conductors () and column conductors () of a touch screen panel (A) for producing a first digital signal (DATA) representative of cross-coupling capacitances (C). Row drive circuitry () superimposes charge transfers from cross-coupling capacitances of the row conductors to a first column conductor to cause the first digital signal to be a convoluted signal. Calibration circuitry () subtracts base line data from the first digital signal to produce a second digital signal (&#x394;DATA) representing touch-induced capacitance change values (&#x394;C). A deconvolution circuit () deconvolutes the second digital signal to produce a digital output () representing a magnitude map of the touch-induced capacitance change values.

Deconvolution-based capacitive touch detection circuit and method

INL error in a SAR ADC () is reduced by providing correction capacitors (B) each having a first terminal connected to a conductor () which is also connected to one terminal of the capacitors of a CDAC (A) and to an input of a comparator () of the SAR ADC. Stored INL error information (A) is utilized to control switches () coupled to second terminals of the correction capacitors to selectively couple them to either a ground voltage (GND) or a reference voltage (V) in response to the stored INL error information so as to reduce the INL errors.

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Tucson, AZ, United States of America

Michael Douglas Snedeker