Amdahl Corporation

Pmc-sierra, Inc.

Michael DeMar Taylor

Joseph A Petolino

Jeffrey A Thomas

John R Kinsel

Michael J Begley

Tom Riordan

Allan J Zmyslowski

Robert M Maier

Kevin L Daberkow

Theodore S Robinson

Christopher D Finan

Ajay K Shah

Richard J Tobias

Kham X Nguyen

Shen H Wang

Mehrzad Kasrazadeh

Jack Chen

Gary N Hammond

Nongnuch Taylor

A single memory element, which may consist of general purpose SRAM chips, implements both tag and data cache memory functions, resulting in an efficient, low cost implementation of high speed external cache memory. In one embodiment, a bank of general purpose RAM used by a microprocessor as an external cache memory stores both cache tags and cache data in separate memory locations. During a read operation, the microprocessor retrieves a cache tag from the bank of general purpose RAM before retrieving corresponding cache data therefrom, and compares the cache tag to a memory address to assess whether requested data resides in the cache memory. The comparison may also be performed concurrently by a system controller device, which may abort the main memory access if a cache hit is detected.

Cache memory architecture with system controller device that compares cache tags to memory addresses received from microprocessor

A single memory element, which may consist of general purpose SRAM chips, is used to implement both tag and data cache memory functions, resulting in an efficient, low cost implementation of high speed external cache memory. In one embodiment, a bank of general purpose random access memory used by a microprocessor as an external cache memory stores both cache tags and cache data in separate memory locations. During a read operation, the microprocessor retrieves a cache tag from the bank of general purpose random access memory before retrieving corresponding cache data therefrom, and compares the cache tag to a memory address to assess whether requested data resides within the cache memory. The microprocessor preferably accesses the bank of general purpose random access memory using a memory mapping function which maps the memory address into a cache tag address and a cache data address.

Cache memory architecture and associated microprocessor design

A system for maintaining the integrity of data stored in a branch prediction mechanism such as a branch target buffer (BTB). Upon encountering a branch instruction, a stream of target instructions is prefetched from cache memory even though the target instruction stream is provided from the BTB. The target instruction stream prefetched from cache is then compared with the predicted target stream selected from the BTB. Upon encountering a mismatch, the predicted instruction stream is canceled and the instructions from cache are utilized. Additionally, predicted branch target addresses are stored in a BTB, similar to a branch history table, and circuitry is provided for comparing the predicted target address with an actual target address during processing of the branch instruction. Again upon encountering a mismatch, instruction from cache as addressed by the actual target address are utilized and predicted instructions are canceled. By utilizing the target address comparison along with the target instruction stream comparison a performance gains is made because mismatches can be detected earlier.

Mechanism for maintaining data coherency in a branch history instruction

In a multiprocessor system with an interleaved memory, predicted busy terms for interleaves of the main store being accessed are sent to each processor in the system, so that they will not waste pipe flows making requests to the busy interleaves. The predicted busy term is lowered before access to the interleaves is complete, to allow for the latency between the time the processor sets up the request and the time the main store system receives it. Contention occurs when several processors request access to the same interleave of main store. To detect deadlocks, a counter for each processor keeps track of the number of consecutive requests from that processor which have been rejected. Once the number reaches a threshold for a first processor, its counter initiates a state machine which inhibits other processors from making requests to the main store until the first processor is successful in gaining access.

Resource contention deadlock detection and prevention

In a data processing system in which a processor has a cache receiving data staged from at least two main memories. Performance is enhanced by providing an indicator identifying the main memory from which data is staged. When data in the cache is destaged, the indicator is used to direct the destaged data to the proper main memory. If an error occur in the indicator, the data will be destaged to each main memory where a check is made on the address of the data to determine whether the main memory is the source of the destaged data. The data is stored in a main memory only if the memory is the source thereof.

Error recovery scheme for destaging cache data in a multi-memory system

An apparatus and method for use in improving cache storage unit utilization during an interlock of an instruction pipeline generates a control signal during one cycle of the interlock if the interlocked instruction may require storage unit management work. In response to the control signal, selector control logic in the storage unit generates a priority signal indicating the interlocked instruction for selection by the storage unit for processing. In response to the control signal and the priority signal, the cache management logic is used during the interlock on the interlocked instruction to prepare for supplying needed data when the interlock is released.

Apparatus and method for improving cache access throughput in pipelined

Bypassing of data from a main storage unit to an instruction and operand processing unit around an intermediate storage unit improves performance in a data processing system. The instruction and operand processing unit supplies requests for operands to the intermediate storage unit or cache. If the line is missing from the cache, the request operand is retrieved from the main storage unit. A bypass data path is connected between the main storage unit, prior to error detecting means in the cache, and the instruction and operand processing unit for transferring requested operands to the instruction and operand processing unit directly. Control, coupled to receive requests for operands and to the instruction and operand processing unit, signals the instruction and operand processing unit to receive the requested operands from the bypass data path when the data includes a requested operand.

Cache move-in bypass

A data processing machine including an instruction and operand processing complex. The instruction and operand processing complex generates results during execution of some instructions. When results are generated, a request to store the results in a high speed cache is generated. The cache receiving the request to store the results includes means for detecting errors in a line in the storage means to which the results are to be stored prior to writing the results to the line. If the line includes an error, a means for correcting the error reads to the line from the cache, corrects the error and restores the line. When the line is restored, the results are written to the cache and a correct ECC code is generated.

Buffer error retry

A data processing machine includes an instruction unit that decodes and organizes a flow of instructions for processing data. In response to certain instructions, the instruction unit generates requests for storage unit resources. In addition, results generated in the instruction unit in response to certain instructions are supplied for storage in the storage unit. The storage unit selects in response to priority logic from completing requests for storage unit resources, including a high speed cache storing data, and a plurality of storage ports for transferring data from the result register to the high speed cache. Each of the storage ports generates requests for access to the high speed cache to transfer the data stored in the respective store ports to the cache. Storage unit priority is determined in part by predicting the fullness of the storage ports.

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San Jose, CA, United States of America

Michael DeMar Taylor