Microtune (texas), Inc.

Csr Technology Inc.

Zoran Corporation

Linear Technology Holding LLC

Michael Dean Womac

Philip T Hisayasu

Jan-Michael Stevenson

Timothy M Magnusen

Kim E Beumer

Thomas L Davis

Richard William Ezell

Tim Magnusen

Armin G Deiss

The subject technology provides for removing a source of delay in a phase-locked loop (PLL) by causing the output rising edge to occur at the same time as the input rising edge. The subject technology replicates the amount of delay experienced along an input reference signal path to the PLL as close as possible using a same circuit configuration and bias circuits as in the input reference signal path. For example, a timing alignment circuit containing a replica circuit adds compensation delay to a negative feedback loop signal to match the feedback loop delay with the reference path delay. The delay of the reference signal path is estimated and added into the replica circuit. The delay characteristics of these two paths negate one another such that the phases of the input reference signal and the feedback loop signal become phase-locked at the input to the PLL.

Multi-chip timing alignment to a common reference signal

Systems and methods which utilize low performance circuitry to provide received signal power detection without unacceptably impacting operation of a receiver circuit are shown. Circuitry utilized to provide received signal power detection according to embodiments comprises circuitry dedicated for use with respect to received signal power detection. Performance of the circuitry of the detection path may be lower than that required of circuitry of the signal processing path. However, performance parameters are selected to provide power detection of desired accuracy (e.g., flat gain) and to meet other performance metrics. Embodiments provide a low performance power detection circuit comprising a low performance tuner configuration. Further embodiments provide a low performance power detection circuit comprising a low performance data converter configuration.

Systems and methods providing signal power detection using low performance circuitry

When dynamically varying a number of active paths in a system, a desired return loss is maintained. Certain embodiments enable dynamic varying of the impedance of parallel signal paths in a system responsive to the number of active ones of the parallel paths dynamically changing, in order to maintain a relatively constant impedance match between a source and the combination of parallel paths, thereby retaining a desired return loss.

System and method for retaining a desired return loss when dynamically varying a number of active paths

A circuit includes a first filter comprising a first inductor coupled to a first variable capacitor, wherein the first filter is associated with a first resonant frequency. The circuit further comprises an amplifier coupled to the first filter and a second filter coupled to the amplifier. The second filter comprises a second inductor coupled to a second variable capacitor, wherein the second filter is associated with a second resonant frequency that is substantially the same as the first resonant frequency. At least a portion of the first filter and at least a portion of the second filter are formed on an integrated circuit.

Integrated channel filter using multiple resonant filters and method of operation

A system for tuning a radio-frequency signal includes a first input path, a second input path, a common reference generator, a selector, a mixer, and a filter. The first input path and the second input path propagate a first single-ended input signal and a second single-ended input signal, respectively, to the selector. The selector converts the first single-ended input signal and the second single-ended input signal into a first differential input signal and a second differential input signal, respectively, using a reference signal generated by the common reference generator. The selector selectively couples one of the first and the second input path to an input of the mixer. The mixer downconverts a selected on of the differential input signals received from the selector. The filter attenuates a portion of the downconverted input signal outside a passband associated with the filter.

Radio-frequency tuner with differential converter

A system for tuning an impedance at a node comprises a first component associated with a first impedance when the first component is operating and a second impedance when the first component is not operating. The system further comprises a second component coupled to the first component at a node. The second component is associated with a third impedance when the second component is operating and a fourth impedance when the second component is not operating. An impedance tuning circuit is coupled to the second component at the node and operable to tune an impedance at the node based at least in part upon a plurality of the first impedance, the second impedance, the third impedance, and the fourth impedance.

System and method for dynamic impedance tuning to minimize return loss

A system for filtering a signal includes a plurality of filter modules coupled in series. Each filter module includes a filter and a variable gain element. Each filter is capable of. receiving an input signal, attenuating a portion of the input signal that is outside a passband associated with the filter, and outputting at least a portion of the input signal that is within the passband associated with the filter. Each variable gain element is capable of receiving a control signal and inducing a gain in an output of the filter based on the control signal.

System and method for providing distributed gain

A method for extending the linear range of operation of an amplifier includes monitoring a transistor voltage of a transistor of an amplifier. The transistor is coupled to a variable current source applying a bias current to the transistor. The method continues by monitoring an output voltage of the amplifier and by determining whether the transistor voltage is within a predetermined range of the output voltage. If the transistor voltage is not within a predetermined range of the output voltage, the method continues by decreasing the bias current applied to the transistor. If the transistor voltage is within a predetermined range of the output voltage and if the bias current has not previously been decreased, the method continues by increasing the bias current applied to the transistor.

Method and system for correcting non-linear response in amplifiers

Disclosed are systems and methods which provide a common bypass node with respect to multiple circuits of an integrated circuit. According to a preferred embodiment, a circuit for filtering bias noise introduced by components of the integrated circuit may be coupled to this common bypass node and bypass bias filtering may be provided with respect to each of the multiple circuits. According to a preferred embodiment, the common bypass node is associated with an external lead or pin of the integrated circuit to thereby facilitate the efficient use of integrated substrate area as well as the efficient use of external interfaces thereof. Additionally, the common bypass node of the preferred embodiment may be utilized in providing cooperative operation of the multiple circuits coupled thereto.

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McKinney, TX, United States of America

Michael Dean Womac