Nokia Mobile Phones Limited

Qualcomm Incorporated

Plessey Overseas Limited

Gec Plessey Telecommunications Limited

Michael David Jager

Vaishnav Srinivas

Harri Honkasalo

Andrew Keith Joy

John S Arnold

Andrew James Pickering

Xavier Loic Leloup

Mahalingam Nagarajan

Christophe Avoinne

Raymond E Oakley

Zhi-Chun Honkasalo (nee Zhu)

A method for providing low latency frequency switching includes operating a first processing component on a first die and operating a second processing component on a second die with the same first clock signal having a first frequency. A request to switch the first frequency to a second, new frequency is received and a second clock signal having the second, new frequency is produced. Data flow between the first die and second die may be stopped. And then the second clock signal is transmitted to a dual phased locked loop architecture on a die interface. A PCLK signal is created from the combined first and second clock signals and an NCLK signal is created from the second clock signal. Next, the PCLK signal is divided and aligned with the NCLK signal. Once the PCLK signal is aligned with the NCLK signal, data flow is resumed between the two dies.

System for providing a low latency and fast switched cascaded dual phased lock loop (PLL) architecture for die-to-die / system-on-chip (SoC) interfaces

Apparatus and method are described for selecting for subsequent use an antenna from a plurality of antennas. The selection is biased in favor of the antenna most likely to receive subsequent signals having best signal quality. In a preferred embodiment the signal quality comprises received signal strength.

Antenna selection control circuitry

Antenna selection control apparatus for a diversity antenna system including at least two antennas. The received power strength is measured from a selected antenna and compared with a reference power level. The reference power level is adjusted depending upon the signal to noise ratio of received signals, and if the selected antenna falls below the adjusted threshold another antenna is selected.

A received and demodulated multi-level signal (32) is corrected for D.C. offset by a feedback loop (34) which applies a correction signal (38) to the multi-level signal (32). Initial coarse correction is provided by feeding the corrected signal (42) into the feedback loop where a low pass filter (36) averages the corrected signal over time and detects departure from zero of this time-averaged signal. After initial coarse correction, finer correction of D.C. offset is provided in a data-aided mode in which detected data values (46) are fed into the feedback loop (34). The method achieves D.C. offset correction without the need to know anything about the data pattern of the received signal (32).

Demodulated radio signals

An asynchronous time division multiplex switching arrangement comprises a serial to parallel converter arranged to receive input packets of data which include routing information, in serial form and convert the packets of data to parallel form. A random access memory is provided in which each packet of data is entered at an addressed location into the memory, and the address is entered in a respective first-in first-out output queue at the tail. The address at the head of the queue is accessed and the packet of data is read from the random access memory into a parallel to serial converter and the packet of data is serially delivered to the associated output.

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Surrey, United Kingdom

Michael David Jager