Altera Corporation

Intel Corporation

Google Inc.

Michael David Hutton

Gregg William Baeckler

David Lewis

Bruce B Pedersen

Herman Henry Schmit

Sinan Kaptanoglu

James G Schleicher

Jinyong Yuan

Babette Van Antwerpen

David Wolk Mendel

Andy Louie Lee

Richard Yuan

James G Schleicher, Ii

Andrew Leaver

Anargyros Krikelis

Sergey Yuryevich Shumarayev

Rakesh H Patel

Sean R Atsatt

Wei-Jen Huang

Tony K Ngai

Dana How

Victor Maruri

Jim Park

Peter J Kazarian

Tim Michael Vanderhoek

Vaughn Betz

Irfan Rahim

Keith Duwel

David Karchmer

David Cashman

Chris Wysocki

Daniel R Mansur

Richard Grenier

Erhard Joachim Pistorius

Pouyan Djahani

Jeffrey Erik Schulz

Rahul Saini

Yean-Yow Hwang

Audrey Kertesz

Martin Langhammer

Richard G Cliff

Chuck Rumbolt

Henry Kim

James Loran Ball

David Neto

Kumara Tharmalingam

Jeffrey Christopher Chromczak

Yi-Wen Lin

Eng Ling Ho

Jeffrey Fox

Bruce B Pederson

Kimberly Anne Bozman

Jason Govig

Gaurav Agrawal

Zhiru Zhang

Greg William Baeckler

Georgios Konstadinidis

Dalon L Westergreen

Herman Henry Schmidt

Swatiben Ruturaj Pathak

Jinyoung Yuan

Yan Lin

Joachim Pistorius

Safeen Huda

Lluis-Miquel Munguia

Bruce B Pedersén

A method and system for controlling performance of a workload partitioned among a plurality of accelerator chips of a multi-chip system. One or more processors may receive performance speed data for each of the accelerator chips, obtain a model of the partitioned workload, determine a portion of the workload that is either overworked or underworked based on the model of the partitioned workload and the performance speed data for each of the plurality of accelerator chips, and adjust a performance speed of an accelerator chip that performs the portion of the partitioned workload that is either overworked or underworked.

Large-scale accelerator system energy performance optimization

A system includes a programmable logic device (PLD) and a processor. The processor determines sets of power values associated with respective portions of a plurality of portions of the PLD. The processor also determines a temperature value for each portion of the plurality of portions based on the sets of power values and platform data associated with the PLD. Additionally, the processor generates a power map indicative of an expected amount of power for each portion of the plurality of portions based on the sets of power values. Furthermore, the processor generates a heat map indicative of an expected temperature value for each portion of the plurality of portions.

Thermal management of integrated circuits

Systems and methods described herein are related to clock signal generation for synchronous electronic circuitry. Power management in electronic devices circuitry may be implemented by scaling the frequency multiple functional modules implemented in the synchronous electronic circuitry. The present disclosure discussed clock generators that may provide frequency scaling of clock signals for functional modules within an electronic device. Moreover, certain clock signal generators may reduce mitigate generation of large currents during frequency scaling by employing circuitry that leads to incremental frequency changes. Circuitry that allows substantially glitchless or reduced-glitch transition between clock rate frequencies are also discussed.

Clock synthesis for frequency scaling in programmable logic designs

The present invention provides a hybrid programmable logic device which includes a programmable field programmable gate array logic fabric and a many-core distributed processing subsystem. The device integrates both a fabric of programmable logic elements and processors in the same device, i.e., the same chip. The programmable logic elements may be sized and arranged such that place and route tools can address the processors and logic elements as a homogenous routing fabric. The programmable logic elements may provide hardware acceleration functions to the processors that can be defined after the device is fabricated. The device may include scheduling circuitry that can schedule the transmission of data on horizontal and vertical connectors in the logic fabric to transmit data between the programmable logic elements and processor in an asynchronous manner.

Hybrid programmable many-core device with on-chip interconnect

Systems and methods for detecting and managing errors in integrated circuits are provided. In one example, a system includes an integrated circuit that includes configuration memory that defines a circuit design implemented by the integrated circuit. The circuit design includes a plurality of regions. Additionally, the system is configured to determine a physical location of an error in the configuration memory and determine a location in a floorplan of the configuration memory that corresponds to the physical location of the error in the configuration memory. The floorplan identifies where the plurality of regions are defined in the configuration memory. The system is configured to determine in which of the plurality of regions the error in the configuration memory has occurred based at least in part on the location in the floorplan. Also, the system is configured to perform a corrective operation based on the location in the floorplan.

Systems and methods for region-based error detection and management in integrated circuits

A method for designing a system on a target device includes mapping a high-level description of the system onto a model of a target device prior to generating a register transfer level description of the system. A visual representation of the mapping is generated.

Method and apparatus for implementing a system-level design tool for design planning and architecture exploration

Systems and methods relating to a programmable circuit. The programmable circuit includes multiple sectors. Each sector includes configurable functional blocks, configurable routing wires, configuration bits for storing configurations for the functional blocks and routing wires, and local control circuitry for interfacing with the configuration bits to configure the sector. The programmable circuit may include global control circuitry for interfacing with the local control circuitry to configure the sector. Each sector may be independently operable and/or operable in parallel with other sectors. Operating the programmable circuit may include using the local control circuitry to interface with the configurations bit and configure the sector. Additionally, operating the programmable circuit may include using the global control circuitry to interface with respective local control circuitry and configure the sector.

Programmable circuit having multiple sectors

In a first mode, a control circuit can implement a circuit design with storage circuits in an integrated circuit by programming configuration memory bits via configuration resources. The storage circuits can be accessed for read and write operations during execution of the implemented circuit design with the integrated circuit. In a second mode, the control circuit can perform read and write access operations at the storage circuits via configuration resources or via an interface circuit and interconnect resources that are allocated to the circuit design implementation. Typical applications for performing access operations at the storage circuits include fault injection and observation, statistical monitoring of the circuit design, initialization and the distribution of certain signals such as reset signals, event sampling, just to name a few.

State visibility and manipulation in integrated circuits

Systems and methods for providing a Network-On-Chip (NoC) structure on an integrated circuit for high-speed data passing. In some aspects, the NoC structure includes multiple NoC stations with a hard-IP interface having a bidirectional connection to local components of the integrated circuit. In some aspects, the NoC stations have a soft-IP interface that supports the hard-IP interface of the NoC station.

Programmable logic device with integrated network-on-chip

A computer-aided design (CAD) tool may identify don't care bits in configuration data. The don't care bits in the configuration data may change polarity without affecting the functionality of the circuit design. The CAD tool may compute an error check code (e.g., parity bits for a two-dimensional parity check) and insert the error check code into the configuration data. As an example, the CAD tool may replace don't care bits in the configuration data with the error code. The configuration data may be stored in configuration memory cells on a programmable integrated circuit, thereby implementing the circuit design with the error code on the programmable integrated circuit. During execution, the programmable integrated circuit may execute error checking and detect and correct errors in the configuration data based on the embedded error code.

Methods and apparatus for embedding an error correction code in storage circuits

An integrated circuit may include a plurality of configuration random access memory (CRAM) sectors that configure logic sectors to perform user-defined functions. The logic circuits configured by the CRAM sectors may vary in their criticality to the operation of the integrated circuit. A prioritized error detection schedule may be provided to error detection circuitry, allowing a more frequent check of sectors that are used to configure logical circuitry that is critical to the operation of the integrated circuit. Upon detecting an error in a given CRAM sector, a sensitivity map may be used to determine the logical location corresponding to the errant CRAM sector. A sensitivity processor may assign a criticality level to the logical location, and appropriate corrective action for the errant CRAM sector may be determined based on the criticality level and the logical location corresponding to the sector.

Prioritized error-detection and scheduling

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Mountain View, CA, United States of America

Michael David Hutton