Advanced Micro Devices Corporation

Kilopass Technology, Inc.

Kilopass Technologies, Inc.

Cypress Semiconductor Corporation

Lattice Semiconductor Corporation

Michael David Fliesler

Jack Zezhong Peng

Mark W Randolph

Fei Ye

Mark T Ramsbey

David Fong

Jianguo Wang

Ian Morgan

Yu Nan Sun

Lee Edward Cleveland

Darlene G Hamilton

Harry Luan

Timothy J Thurgate

Jun Li

Richard C Blish

Jeffery Scott Hunt

Glen Arnold Rosendale

Yuan Tang

John M Callahan

Nancy S Leong

Tiao-Hua Kuo

Hemanshu T Vernenker

Chung K Chang

David Michael Rogers

Len Toyoshiba

Morgan Andrew Whately

Muthukumar Nagarajan

Colin D Hatchard

David Robert Lindley

Mimi Xuefeng Qian

Zhongshan Liu

Zhongshang Liu

Paohua Kuo

Vinod Rajan

Disclosed is a dynamic detector to detect an environmental condition including a power-supply level relative to a predetermined threshold signal during a training phase; and an adjustable buffer, coupled with the dynamic detector, configured to adjust output drive strength during the training phase in response to the detected environmental condition.

Method and apparatus for dynamically detecting environmental conditions and adjusting drive strength in response to the detecting

A programmable memory cell formed useful in a memory array having column bitlines and row wordlines. The memory cell including a breakdown transistor having its gate connected to a program wordline and a write transistor connected in series at a sense node to said breakdown transistor. The gate of the write transistor is connected to a write wordline. Further, a first sense transistor has its gate connected to the sense node. A second sense transistor is connected in series to the first sense transistor and has its gate connected to a read wordline. The second sense transistor has its source connected to a column bitline.

3.5 transistor non-volatile memory cell using gate breakdown phenomena

A method of programming a memory cell is disclosed. The memory cell comprises a select transistor and a data storage element. The method comprises allowing current to flow through the data storage element until a predetermined current or voltage is detected. If the current or voltage exceeds a threshold, then the programming is deemed complete.

Methods and circuits for programming of a semiconductor memory cell and memory array using a breakdown phenomenon in an ultra-thin dielectric

A method of testing the programmability of a memory cell is disclosed. The memory cell comprises a select transistor and a data storage element. The method comprises applying a test voltage across the data storage element. The select transistor is turned on. Finally, a current flow through the data storage element when the test voltage is applied is measured. A test positive signal is indicated if the current flow is greater than a reference.

Methods and circuits for testing programmability of a semiconductor memory cell and memory array using a breakdown phenomenon in an ultra-thin dielectric

A cell that can be used as a dynamic memory cell for storing data or a field programmable gate array (FPGA) cell for programming is disclosed. The cell includes a capacitor having a first terminal connected to a column bitline and a second terminal connected to a switch control node. A select transistor has a gate connected to the read bitline, a source connected to the switch control node, and a drain connected to a row wordline. The switch control node stores data as a voltage indicative of a one or a zero.

Combination field programmable gate array allowing dynamic reprogrammability and non-votatile programmability based upon transistor gate oxide breakdown

A programmable memory cell comprised of a transistor located at the crosspoint of a column bitline and a row wordline is disclosed. The transistor has its gate formed from the column bitline and its source connected to the row wordline. The memory cell is programmed by applying a voltage potential between the column bitline and the row wordline to produce a programmed n+ region in the substrate underlying the gate of the transistor. Further, a gate dielectric of the transistor has a higher breakdown voltage near the source connected to the row wordline than its drain.

High density semiconductor memory cell and memory array using a single transistor and having variable gate oxide breakdown

One aspect of the present invention provides a process for forming IC devices with ESD protection transistors. According to one aspect of the invention, an ESD protection transistor is provided with a light doping and then, after forming spacers, a heavy doping. The heavy doping with spacers in place can lower the sheet resistance, enhance the bipolar effect for the transistor, reduce the transistor's capacitance, and reduce the junction breakdown voltage, all without causing short channel effects. The invention thereby provides ESD protection transistors that are compact, highly sensitive, and fast-switching. The spacers can be formed at the same time as spacers for other transistors, such as other transistors in a peripheral region of the device.

ESD implant following spacer deposition

An ESD protection device is provided for an integrated circuit. The ESD protection device includes a power supply clamp device formed from a diode and coupled between a first power supply V and a second power supply V . An input protection device is also provided which is formed from a diode coupled between an input pad and the first power supply and a second diode coupled between the input pad and a second power supply. The diodes have an adjusted reverse breakdown voltage that is higher than the voltage supply V used to power the peripheral circuitry that drives circuitry within a core of the integrated circuit. The adjusted reverse breakdown voltage is also lower than the breakdown voltage of gate oxide layers used within the peripheral circuitry.

Diode fabrication for ESD/EOS protection

A method of manufacturing a flash memory semiconductor device that eliminates the step of forming sidewall spacers on n-channel and p-channel transistor gate structures. Resist spacers having a dimension of G &plus;2S are formed on n-channel transistor gate structures and an N implant is performed to form N implant is performed to form N regions in the n-channel substrate region. Resist spacers having a dimension of G &plus;2S are formed on p-channel transistor gate structures and a P implant is performed to form P regions in the p-channel substrate region.

Photoresist spacer process simplification to eliminate the standard polysilicon or oxide spacer process for flash memory circuits

Method for bond pad crater jeopardy identification in integrated circuits, and apparatus which performs the method. The gate or gates of a transistor or transistors of an ESD device are formed under each bond pad in the integrated circuit device. Connected to the transistor is circuitry for determimg the electrical, and hence mechanical, integrity of the transistor. A reduction in current through the transistor, by reason of microcrack formation in the several layers under the transistor causing a gate or gates of the transistor to crack and fail, may detected, Location of at least a portion of the ESD device, for example the above transistor, reduces overall chip area by increasing device density.

Method and apparatus for achieving bond pad crater sensing and ESD protection integrated circuit products

In a non-volatile memory comprising a region,for core memory cells and a peripheral region,on a substrate,, a method for improving electrostatic discharge (ESD) robustness of the non-volatile memory comprises the steps of lightly doping the source and drain regions,and,of a peripheral transistor,in the peripheral region,with a first n-type dopant, providing a double diffusion implant mask,having an opening over the region,for the core memory cells and also an opening,over the peripheral region,, and performing a double diffusion implantation through the opening,over the peripheral region,. In an embodiment, the step of performing the double-diffusion implantation comprises the steps of implanting a second n-type dopant comprising phosphorus into the source and drain regions,and,, and implanting a third n-type dopant comprising arsenic into the source and drain regions,and,subsequent to the step of implanting the second n-type dopant.

Method for improving electrostatic discharge (ESD) robustness

An integrated circuit including an array of flash EEPROM memory cells wherein overerase correction is provided after application of each erase pulse.

Overerase correction for flash memory which limits overerase and

Growing community of inventors

Santa Cruz, CA, United States of America

Michael David Fliesler