Unisys Corporation

Sperry Corporation

Sperry Rand Corporation

Michael Danilenko

Larry L Byers

John T Rusterholz

Lawrence R Fontaine

Archie E Lahti

Clarence W DeKarske

Louis B Bushard

David J Tanglin

Arthur Flets Boehm

John E Larson

James Robert Davis, Jr

Charles G Baumann, Jr

A multi-function high speed sequencer is provided in a high speed instruction processor. The high speed sequencer comprises a first input latch coupled to logic signals for producing a first sequence signal. A chain of alternately clocked even and odd principal latches are coupled to the output of the first input latch to produce even and odd principal sequence signals for accessing a high speed MSU. A plurality of staging latches are coupled between the odd and the even principal latches for producing even and odd secondary sequence signals for accessing a slower speed MSU.

Multi-function timing sequencer for different speed main storage units

A cache buffer for a multiprocessor system utilizes two RAMs to store validity bits. Use of these RAMs greatly reduces chip area required to implement the validity buffer and reduces interconnection foil (printed connectors) and hence propagation time. An initial clear state is written into all of the memory locations of both RAMs. One of the RAMs then becomes the active validity bit RAM and the other a standby. When a fast invalidate command is received, upon an invalidate parity error indication from a memory readout, for example, the standby RAM is switched to the active RAM, and the validity bits of the formerly active RAM are cleared in sequential write cycles after it is switched to a standby state.

Dual cache RAM for rapid invalidation

A series of instructions N, N+1, N+2, etc. are issued by an instruction buffer 14 at a fixed clock rate in a pipelined method to parallel instruction flow path 6 and control word flow path 8, each path including a serial coupled holding register 20, 21, an instruction register 18, 19 and a function register 16, 17. If instruction N is a jump instruction, it and the related control word, when stored in the function registers 16, 17 causes the jump target instruction and the related control word of the jump instruction N to be entered into the holding register 20, 21. If the jump instruction N jump conditions are satisfied, the jump target instruction and related control word are written into the instruction registers 18, 19 and then into the function registers 16, 17 to be executed by the associated system.

Electronic data processing system overlaid jump mechanism

A method and a means of increasing the performance of an instruction buffer in a digital data processing system is disclosed. The improvement is accomplished by by-passing the content addressable memory operation which has heretofore been utilized to access page addresses in the instruction buffer. As each word included on the same page was accessed, the CAM was repetitiously activated even though it was accessing the same page. In the present system, word accesses made to the same page are handled in a much improved manner. In the present system, a comparator is implemented in the system which compares the presently reference page with the previously referenced word, so that when a match is noted, i.e., the same page is indicated, the CAM is bypassed and successive requests made to the same page are satisfied from the instruction buffer by a validity designator which designates that the presently referenced word is the correct one.

Instruction buffer for a digital data processing system

A memory accessing system for reading or writing consecutive addressable words is described for use in a set associative memory system. Two high speed buffer memories store words read in blocks from a slower main memory. One buffer stores even addressed words and the other stores odd addressed words. Each buffer memory has a tag memory associated with it for indicating data words stored in the buffer memories. A comparison circuit compares two addresses to be accessed to the tags and provides hit or miss signals for each address indicating residency or non-residency in the buffers. If both addressed words are resident, access to read or write the two consecutive data words is accomplished simultaneously. If either or both addressed words are not resident in the buffers, the main memory is accessed to acquire a block or blocks containing the missing addressed word or words. Consecutively addressed data words can occur within a block or across block boundary. The system examines the addresses and gives an indication when a block boundary crossing is to occur, and provides accessing to read or write sequentially addressed data words across the block boundary crossing simultaneously.

Buffer memory referencing system for two data words

A priority system in which eight priority request signals from eight associated requestors R7-R.phi. may simultaneously request access to an associated memory unit and may be honored in one of several priority modes. In a first mode the requestors R7-R.phi. are honored pre-emptively or in a numerically descending ordered manner in which priority selection is from the highest ordered priority requestor R7 first to the lowest ordered priority requestor R.phi. last. In a second mode the requestors R7-R.phi. are functionally divided into 4 groups of 2 requestors per group in which the priority request signals from the 4 groups 4, 3, 2, 1 of requestors may be selected pre-emptively, e.g., groups 4; 3; 2; 1 of requestors R7, R6; R5, R4; R3, R2; R1, R.phi. respectively, are honored in a numerically descending ordered manner in which the priority selection is from the highest priority group 4 first to the lowest priority group 1 last and in which priority between requestors within a group, e.g., requestors R5, R4 in group 3, is rotational such that in the event both requestors R5, R4 are requesting priority the requestor not last honored is honored first, e.g., if the higher ordered requestor R5 was last honored and requestors R5, R4 are now both requesting access to the memory storage unit, the order of priority will be rotated with the lower ordered requestor R4 having priority over the higher ordered requestor R5. Rotational priority between adjacent groups of requestors is also provided.

Growing community of inventors

West St. Paul, MN, United States of America

Michael Danilenko