Raytheon Company

Hughes Aircraft Company

Michael D Vahey

William D Farwell

Lloyd J Lewins

Kenneth E Prager

Lloyd Frederick Linder

Ian S Robinson

Harry B Marr

John D Bloomer

Clifford W Meyers

Julia L Karl

George K Tucker

Dennis J Finn

Michael J Campbell

Rex W Vedder

Ian N Robinson

An imaging platform minimizes inter-frame image changes when there is relative motion of the imaging platform with respect to the scene being imaged, where the imaging platform may be particularly susceptible to image change, especially when it is configured with a wide field of view or high angular rate of movement. In one embodiment, a system is configured to capture images and comprises: a movable imaging platform having a sensor that is configured to capture images of a scene, each image comprising a plurality of pixels; and an image processor configured to: digitally transform captured images with respect to a common field of view (FOV) such that the transformed images appear to be taken by a non-moving imaging platform, wherein the pixel size and orientation of pixels of each transformed image are the same. A method for measuring and displaying 3-D features is also described.

Correcting frame-to-frame image changes due to motion for three dimensional (3-D) persistent observations

A data flow controller for reconfigurable computers. The novel data flow controller includes a first circuit for selecting one of a plurality of operating conditions and a second circuit for determining if the selected condition is met and outputting a control signal accordingly. In an illustrative embodiment, the operating conditions include: when all enabled data available signals are asserted and all enabled space available signals are asserted; when any enabled data available signal is asserted and all enabled space available signals are asserted; when all enabled data available signals are asserted and any enabled space available signal is asserted; and when any enabled data available signal is asserted and any enabled space available signal is asserted. By allowing a configurable element to operate under different possible conditions, data flow signals can also then be used to control what operation the element performs, in addition to controlling when.

Means of control for reconfigurable computers

A digital signal processing apparatus includes a digital circuit device having one or more elements configured to process digital data; a power supply configured to deliver a controllable operating voltage for the one or more elements; control logic configured to receive feedback signals from each of the one or more elements, the feedback signals indicative of a rate at which data is moving through each individual element; and the control logic configured to output a control signal to the power supply so as to cause the power supply to reduce the operating voltage for the one or more elements responsive to a decreasing workload detected therein, and to cause the power supply to increase the operating voltage for the one or more pipelines responsive to an increasing workload detected therein.

Minimizing power consumption in asynchronous dataflow architectures

A mixed technology microcircuit including a first circuit fabricated on a first layer with a first technology and a second circuit fabricated on a second layer with a second technology. In the illustrative embodiment, the first circuit is fabricated with silicon germanium (SiGe) technology and the second circuit is fabricated with complementary metal-oxide semiconductor (CMOS) technology. In an illustrative application, the first circuit includes a high-speed data receiver and a high-speed data transmitter. In the illustrative implementation, the data receiver includes a line receiver, a data and clock recovery circuit, and a demultiplexer and the data transmitter includes a multiplexer, a data and clock encoding circuit, and a line driver.

Mixed technology microcircuits

A data-flow architecture and software environment for high-performance signal and data procesing. The programming environment allows applications coding in a functional high-level language 20 which a compiler 30 converts to a data-flow graph form 40 which a global allocator 50 then automatically partitions and distributes to multiple processing elements 80, or in the case of smaller problems, coding in a data-flow graph assembly language so that an assembler 15 operates directly on an input data-flow graph file 13 and produces an output which is then sent to a local allocator 17 for partitioning and distribution. In the former case a data-flow processor description file 45 is read into the global allocator 50, and in the latter case a data-flow processor description file 14 is read into the assembler 15. The data-flow processor 70 consists of multiple processing elements 80 connected in a three-dimensional bussed packet routing network. Data enters and leaves the processor 70 via input/output devices 90 connected to the processor. The processing elements are designed for implementation in VLSI (Very large scale integration) to provide realtime processing with very large throughput. The modular nature of the computer allows adding more processing elements to meet a range of throughout and reliability requirements. Simulation results have demonstrated high-performance operation, with over 64 million operations per second being attainable using only 64 processing elements.

Data-flow multiprocessor architecture with three dimensional multistage

Growing community of inventors

Manhattan Beach, CA, United States of America

Michael D Vahey