Intel Corporation

Other

Cascade Design Automation Corporation

Michael D Upton

David J Sager

Glenn J Hinton

Darrell D Boggs

Thomas D Fletcher

James D Allen

David W Burns

Edward Thomas Grochowski

Per H Hammarlund

Alan Beecher Kyker

George Zacharias Chrysos

Douglas M Carmean

Robert F Krick

Chan W Lee

Andrew Thomas Forsyth

Dennis Ryan Bradford

Amit A Merchant

Chunhui Zhang

Zhongying Zhang

Lisa K Wu

Brent E Lince

Aravindh Baktha

Bryon George Conley

Harish Kumar

Gregory Mont Thornton

Venkat K S Venkatraman

Sherece Upton

Duncan Waruingi

Thomas F Rossman

Jay S Fuller

Mohammed L Al-Aqrabawi

Dean P Frazier

Kendall C Russell

James Allen

The parking space availability system is configured for use with a parking facility that further comprises a plurality of parking spaces. Each parking space contained within the plurality of parking spaces comprises an occupancy status selected from the group consisting of an open parking space and an occupied parking space. The parking space availability system comprises a surveillance device, one or more mapping devices and a wireless communication facility. The wireless communication facility wirelessly connects each of the one or more mapping devices to the surveillance device. The surveillance device forwards the location of each identified open parking space to the one or more mapping devices using the wireless communication facility. Each of the one or more mapping devices is used by a user to locate the identified open parking spaces.

Parking space availability system

An apparatus and method are described for performing efficient gather operations in a pipelined processor. For example, a processor according to one embodiment of the invention comprises: gather setup logic to execute one or more gather setup operations in anticipation of one or more gather operations, the gather setup operations to determine one or more addresses of vector data elements to be gathered by the gather operations; and gather logic to execute the one or more gather operations to gather the vector data elements using the one or more addresses determined by the gather setup operations.

Apparatus and method for efficient gather and scatter operations

Disclosed herein is a generational thread scheduler. One embodiment may be used with processor multithreading logic to execute threads of executable instructions, and a shared resource to be allocated fairly among the threads of executable instructions contending for access to the shared resource. Generational thread scheduling logic may allocate the shared resource efficiently and fairly by granting a first requesting thread access to the shared resource allocating a reservation for the shared resource to each other requesting thread of the executing threads and then blocking the first thread from re-requesting the shared resource until every other thread that has been allocated a reservation, has been granted access to the shared resource. Generation tracking state may be cleared when each requesting thread of the generation that was allocated a reservation has had their request satisfied.

Generational thread scheduler using reservations for fair scheduling

A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.

Processor having execution core sections operating at different clock rates

In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.

Method and apparatus for assigning thread priority in a processor or the like

A context identifier is used in a cache memory apparatus. The context identifier may be written into the tag of a cache line or may be written as an addition to the tag of a cache line, during cache write operation. During a cache read operation, the context identifier of as issued instruction may be compared with the context identifier in the cache line's tag. The cache line's data block may be transferred if the context identifiers and the tags match.

Use of a context identifier in a cache memory

In a multi-threaded processor, thread priority variables are set up in memory. According to an embodiment of the present invention, several conditions are monitored so as to determine an indication of instruction side starvation may be approaching. If such starvation is approaching, the starvation is resolved upon the expiration of a threshold counter or the like.

Determining whether thread fetch operation will be blocked due to processing of another thread

According to one aspect of the invention, a microprocessor is provided that includes an execution core, a first replay mechanism and a second replay mechanism. The execution core performs data speculation in executing a first instruction. The first replay mechanism is used to replay the first instruction via a first replay path if an error of a first type is detected which indicates that the data speculation is erroneous. The second replay mechanism is used to replay the first instruction via a second replay path if an error of a second type is detected which indicates that the data speculation is erroneous.

Processor having replay architecture with fast and slow replay paths

Determination of approaching instruction starvation of threads based on a plurality of conditions

A request received from a requester to access a processor cache or register file or the like is buffered, by storing requestor identification, request type, address, and a status of the request. This buffered request may be forwarded to the cache if it has the highest priority among a number of buffered requests that also wish to access the cache. The priority is a function of at least the requestor identification, the requester type, and the status of the request. For buffered requests which include a read, the buffered request is deleted after, not before, receiving an indication that the requestor has received the data read from the cache.

Processing requests to efficiently access a limited bandwidth storage area

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Portland, OR, United States of America

Michael D Upton