Freescale Semiconductor,inc.

Motorola Corporation

International Business Machines Corporation

Other

Oracle International Corporation

Michael D Snyder

Gary L Whisenhunt

William C Moyer

Shayan Zhang

Klas Magnus Bruce

Rajesh Bhikhubhai Patel

Andrew Christopher Russell

Kumar K Gala

Becky Bruce

Matt B Smittle

James David Burnett

Cathy May

Belliappa Manavattira Kuttanna

Sanjay Raghunath Deshpande

Zheng Xu

Sergio Schuler

Thomas Alan Hoy

David C Holloway

Magnus K Bruce

Giles R Frazier

Ravindraraj Ramaraju

Bradly George Frey

Prashant U Kenkare

Suresh Kumar Venkumahanti

James Xenidis

Hema Ramamurthy

Michael Julio Garcia

Trinh Huy Nguyen

David W Todd

Brian Keith Reynolds

Kent P Fancher

Jamshed Jalal

Brett Olsson

Charles P Roth

Paul Joseph Jordan

Keith E Diefendorff

Mark Luttrell

Bradford Lawrence Hunter

David R Bearden

Edward John Silha

Bryan D Marietta

Pradeep Kumar Dubey

Daniel L Bouvier

Bradley Gene Burgess

John D Pape

Troy L Cooper

Ronald Ray Hochsprung

Jack M Higman

Hunter Ledbetter Scales, Iii

Jason T Nearing

Steven C Sullivan

James C Holt

Brian C Grayson

Suraj Bhaskaran

David Burnett

Leick D Robinson

Kathryn C Stacer

David F Greenberg

Paul B Rawlins

Syed R Rahman

David M Thompson

Ravindraj Ramaraju

Hassan F Al-Sukhni

Bradford Byron Beavers

Random numbers within a processor may be scarce, especially when multiple hardware threads are consuming them. A local random number buffer can be used by an execution core to better manage allocation and consumption of random numbers. The buffer may operate in a number of modes, and allow any hardware thread to use a random number under some conditions. In other conditions, only certain hardware threads may be allowed to consume a random number. The local random number buffer may have a dynamic pool of entries usable by any hardware thread, as well as reserved entries usable by only particular hardware threads. Further, a user-level instruction is disclosed that can be stored in a wait queue in response to a random number being unavailable, rather than having the instruction's request for a random number simply be denied. The random number buffer may also boost performance and reduce latency.

Storage, access, and management of random numbers generated by a central random number generator and dispensed to hardware threads of cores

For use in a data processing system comprising a processor configured to execute a first set of instructions corresponding to a first thread and a second set of instructions corresponding to a second thread, a method is provided. The method comprises in response to execution of a debug related instruction by the first thread while executing the first set of instructions, generating a debug event for processing by the second thread, wherein processing the debug event comprises causing a halting operation related to the processor.

Debug instruction for execution by a first thread to generate a debug event in a second thread to cause a halting operation

A data processing system having a processor and a target device processes decorated instructions (i.e. an instruction having a decoration value). A device of the data processing system such as the processor sends transactions to the target device over a system interconnect. A decorated storage notify (DSN) transaction includes an indication of an instruction operation, an address associated with the instruction operation, and a decoration value (i.e. a command to the target device to perform a function in addition to a store or a load). The transaction on the system interconnect includes an address phase and no data phase, thereby improving system bandwidth. In one form the target device (e.g. a memory with functionality in addition to storage functionality) performs a read-modify-write operation using information at a storage location of the target device.

Data processor for processing a decorated storage notify

A technique for indicating a safe shared resource condition with respect to a disabled thread provides a mechanism for providing a fast indication to other hardware threads that a temporarily disabled thread can no longer impact shared resources, such as shared special-purpose registers and translation look-aside buffers within the processor core. Signals from pipelines within the core indicates whether any of the instructions pending in the pipeline impact the shared resources and if not, then the thread disable status is presented to the other threads via a state change in a thread status register. Upon receiving an indication that a particular hardware thread is to be disabled, control logic halts the dispatch of instructions for the particular hardware thread, and then waits until any indication that a shared resource is impacted by an instruction has cleared. Then the control logic updates the thread status to indicate the thread is disabled.

Indicating disabled thread to other threads when contending instructions complete execution to ensure safe shared resource condition

A processor provides memory request and a coherency state value for a coherency granule associated with a memory request. The processor further provides either a first indicator or a second indicator depending on whether the coherency state value represents a cumulative coherency state for a plurality of caches of the processor. The first indicator and the second indicator identify the coherency state value as representing a cumulative coherency state or a potentially non-cumulative coherency state, respectively. If the second indicator is provided, a transaction management module determines whether to request the cumulative coherency state for the coherency granule in response to receiving the second indicator. The transaction management module then provides an indicator of the request for the cumulative coherency state to the processor in response to determining to request the cumulative coherency state. Otherwise, the transaction management module processes the memory transaction without requesting the cumulative coherency state.

System and method for processing potentially self-inconsistent memory transactions

Complex on-chip interconnect fabrics, particularly those that include point-to-point interconnects and coherent routing networks, can present significant challenges for conventional trace techniques that may be applied in an effort to efficiently provide an external debugger with visibility into on-chip interconnect transactions. Embodiments described herein generate and supply separate in-circuit-trace messages including address messages and data messages, which are sent out (i.e., off-chip) to external debug tools generally without delay and coincident with the distinct, but related, trace events within address and data paths of the interconnect fabric. These separate message instances embed appropriate tag and mark values to allow the message instances to be post-processed and correlated by the external debug tools so as to reconstruct the transaction information for operations performed in the on-chip interconnect.

Tracing support for interconnect fabric

A plurality of new snoop transaction types are described. Some include address information in the requests, and others include cache entry information in the requests. Some responses include tag address information, and some do not. Some provide tag address content on the data bus lines during the data portion of the transaction. These new snoop transaction types are very helpful during debug of a data processing system.

Method and apparatus for cache transactions in a data processing system

A technique for scheduling execution of threads at a processor is disclosed. The technique includes executing a thread de-emphasis instruction of a thread that de-emphasizes the thread until the number of pending memory transactions, such as cache misses, associated with the thread are at or below a threshold. While the thread is de-emphasized, other threads at the processor that have a higher priority can be executed or assigned system resources. Accordingly, the likelihood of a stall in the processor is reduced.

Thread de-emphasis instruction for multithreaded processor

A data processing system having a processor and a target device processes decorated instructions (i.e. an instruction having a decoration value). A device of the data processing system such as the processor sends transactions to the target device over a system interconnect. The transactions include an indication of an instruction operation, an address associated with the instruction operation, a decoration value (i.e. a command to the target device to perform a function in addition to a primary function of the executed instruction), and access permissions associated with the address. The target device (e.g. a memory with functionality in addition to storage functionality) determines whether a decoration operation specified by the decoration value is permissible based on the received access permissions. The target device performs the decoration operation if appropriate permissions exist.

Permissions checking for data processing instructions

Processor with hardware thread control logic indicating disable status when instructions accessing shared resources are completed for safe shared resource condition

A first thread enters a polling loop to wait for a signal from a second thread before processing instructions dependent on the polling loop. When entering the polling loop, the first thread sets a reservation for a predetermined memory address. The first thread then executes a reservation-based instruction that can change the execution state of the first thread. Reservation circuitry of the processing device that was executing the first thread monitors the reservation. In the event that the reservation cleared, such as by the second thread modifying data at the predetermined memory address, the first thread is reinstated to its prior execution state. By using a hardware reservation mechanism to monitor for clearing of a set reservation, repeated memory accesses to the memory address by the first thread can be minimized or avoided while in the polling loop and other threads can be allowed to execute at the processing device with reduced interference from the waiting thread.

Polling using reservation mechanism

A memory system has a first memory having an array of memory cells that includes a redundant column. The redundant column substitutes for a first column in the array. The first column includes a test memory cell. The array receives a power supply voltage. The test memory cell becomes non-functional at a higher power supply voltage than the memory cells of the array. A memory controller is coupled to the first memory and is for determining if the test memory cell is functional at a first value for the power supply voltage. This is useful in making decisions concerning the value of the power supply voltage applied to the array.

Methods for testing a memory embedded in an integrated circuit

Integrated circuit having an embedded memory and method for testing the memory

A system is used to determine if a sum of a first operand and a second operand is the same as a third operand wherein a comparison to the third operand is of variable length. This is particularly useful in a content addressable memory (CAM) where the likelihood of hit is commonly improved over a set associative cache and allows for the CAM to identify different things. For example, an entry can be one length to identify a page of a memory and another entry be a different length to identify a page of memory. This is better understood by reference to the following description and the drawings.

Technique for determining if a logical sum of a first operand and a second operand is the same as a third operand

A processor implementation supports selection of an execution mode for debug instruction instances based on respective addresses thereof in addressable memory can provide an attractive mechanism for executing debug instructions in a way that allows some instances of the instructions to operate with debug semantics while suppressing other instances by executing them with no-operation (NOP) semantics. In some embodiments, selection of operative execution semantics may be based on attributes of a memory page in which a particular debug instruction instance resides. In some embodiments, portions of an address space may be delimited (e.g., using values stored in bounding registers and addresses of particular debug instruction instances compared against the delimited portions to select appropriate execution semantics. In some embodiments, both types of evaluations may be used in selecting appropriate execution semantics for a particular debug instruction instance.

Qualification of conditional debug instructions based on address

Growing community of inventors

Austin, TX, United States of America

Michael D Snyder