Bull Hn Information Systems, Inc.

Honeywell Information Systems Inc.

Michael D Smith

Richard A Lemay

William E Woods

Robert C Miller

John L Curley

Theodore R Staplin, Jr

Llewelyn S Dunwell

A data processing system includes a number of subsystems coupled in common to a system bus. The subsystems communicate with each other by sending commands to each other via the system bus. Channel numbers identify the subsystems. One subsystem includes apparatus for receiving commands requiring a priority interrupt by storing vectors in a random access memory. These vectors which are addressed by the channel number of the interrupting subsystem indicate the offset to be added to the base address of an exception vector table. The exception vector stores the starting address in a memory of the requested interrupt routine.

Microprocessor vectored interrupts

A data processing system includes a number of subsystems all coupled in common to a system bus and communicate with each other by sending and receiving commands sent over the system bus. A central processing subsystem includes a response memory for storing indication of the responses sent by the receiving subsystem when receiving commands sent by the central processing subsystem. The responses include an acknowledge response, a not acknowledge response or no response--a timeout. Storing the acknowledge response and the timeout will enable the programmer to determine which of the three responses was received.

Storage of input/output command timeout and acknowledge responses

A data processing system includes a central processor unit (CPU), a main memory and a memory management unit (MMU). Information is stored in main memory in segments, each segment being identified by a segment descriptor stored in a translation table in the MMU. Logical addresses from the CPU address segment descriptors in the MMU's translation table. These segment descriptors include the physical address of the location in main memory of the first word of the segment. If the segment descriptor is not in the translation table location, then the MMU operation is suspended while the segment descriptor is demand fetched from main memory.

Hardware demand fetch cycle system interface

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Michael D Smith