Lsi Logic Corporation

Kawasaki Steel Corporation

Kawasaki Microelectronics, Inc.

Other

Kawasaki Lsi U.s.a., Inc.

Michael D Rostoker

Nicholas F Pasch

James S Koford

Ranko L Scepanovic

Edwin R Jones

Ashok K Kapoor

Douglas B Boyle

Alexander E Andreev

Stanislav V Aleshin

Alexander S Podkolzin

John P Daane

Gobi R Padmanahben

Joe Zelayeta

D Tony Stelliga

Carlos Dangelo

Valeriy B Kudryavtsev

Mark R Schneider

Sandeep Jaggi

Sanjay M Desai

Valeriv B Kudryavtsev

Daniel R Watkins

Dorothy A Heim

Chok J Chia

Edwin M Fulcher

David Gluss

Joel Silverman

Kumaraguru Muthukumaraswamy

Jerry Erh Chow

Sushant Verman

Richard Egan

Abraham Fong Yee

Vijay K Nagasamy

Seng-Sooi Allen Lim

Owen S Bair

Willem A Engelse

Jen-Hsun Huang

Doron Mintz

Richard Brossart

David E Sanders

Kumaraguru Muthujumaraswathy

William C Schneider

Scott A Macomber

Dave Paolino

John Pierre McCormick

Conrad J Dell'Oca

Joseph H Joroski

Daniel J Lincoln

Tom Ley

Manouchehr Vafai

Peter K Yu

Kurt Raymond Raab

Yin Chang

Tom Harrington

Keiichi Kawana

Ashook K Kapoor

Paul Bergantino

Anthony Stelliga

Edwin E Jones

Valerity B Kudryavtsev

A protocol translation cable assembly includes a first connector having a first plurality of pins, a second connector having a second plurality of pins, and an electrical cable coupling the first connector to the second connector, where the electrical cable includes a plurality of conductors. The protocol translation cable assembly further includes translation circuitry coupled to at least some of the plurality of wires of the electric cable at points between the first plurality of pins of the first connector and the second plurality of pins of the second connector. The translation circuitry preferably derives its power from the electrical cable such that separate power supplies are not required. The cable assembly therefore provides transparent 'plug-and-play' capabilities.

Plug-and-play cable with protocol translation

Automated photolithography of integrated circuit wafers is enabled with a processor connected to a Rayleigh derator, a form factor generator, a logic synthesizer, a layout generator, a lithography module and a wafer process. The Rayleigh derator receives manufacturing information resulting from yield data in the wafer process, and this manufacturing data is then used to derate the theoretical minimum feature size available for etching wafer masks given a known light source and object lens numerical aperture. This minimum feature size is then used by a form factor generator in sizing transistors in a net list to their smallest manufacturable size. A logic synthesizer then converts the net list into a physical design using a layout generator combined with user defined constraints. This physical design is then used by the mask lithography module to generate wafer masks for use in the semiconductor manufacturing. Manufacturing data including process and yield parameters is then transferred back to the Rayleigh processor for use in the designing of subsequent circuits. In this way, a direct coupling exists between the measurement of wafer process parameters and the automated sizing of semiconductor devices, enabling the production of circuits having the smallest manufacturable device sizes available for the given lithography and wafer process.

Automating photolithography in the fabrication of integrated circuits

An integrated circuit architecture for multimedia processing. A single integrated circuit (IC) operates as a system or subsystem, and is adaptable to processing a variety of multimedia algorithms, whether proprietary or open. Hard macros, either analog or digital, can be incorporated. The IC can also contain audio/video CODECs to suit different standards, as well as other peripheral devices which may be required for multimedia applications. An electronic component (e.g., integrated circuit) incorporating the technique is suitably included in a system or subsystem having electrical functionality, such as general purpose computers, telecommunications devices, and the like.

Multimedia interface having a processor and reconfigurable logic

An improved load restraint system and method for protecting and supporting loads, such as cargo, especially during transit movement. The load restraint system and method compensates for various attitude, altitude and ambient pressure changes while maintaining sufficient restraining supportive force on the cargo. One embodiment maintains ambient pressure sensing with pressure/volume fluid compensation to an inflatable bladder responsive to ambient pressure changes within the cargo container. Another embodiment permits inflation of a rigidifying bladder to provide in-situ rigid support for the cargo, included during ambient pressure changes within the cargo container.

Load restraint method

A plurality of devices communicate information over a wireless network at radio frequencies. The information includes digital audio, video and data. Bandwidth among the devices is dynamically allocated, the allocation being based upon the needs of the devices. One embodiment of the wireless network is a Time Division Multiple Access network. Another embodiment is a wireless Ethernet. Yet another embodiment is a Frequency Division Multiplexed network.

Method and apparatus for increasing the effective bandwidth within a digital wireless network

Load restraint system and method

A physical design automation system produces an optimal placement of microelectronic components or cells on an integrate circuit chip. An initial population of possible cell placements is generated, and repeatedly altered using simulated on or other fitness improvement algorithm to progressively increase the fitnesses (decrease the costs) of the placements. After each alteration step, the fitnesses of the placements are calculated, and less fit placements are discarded in favor of more fit placements. After a termination criterion is reached, the placement having the highest fitness is designated as the optimal placement. Two or more fitness improvement algorithms are available, and are optimally switched from one to the other in accordance with an optimization criterion to maximize convergence of the placements toward the optimal configuration.

Optimization processing for integrated circuit physical design automation system using optimally switched fitness improvement algorithms

An efficient DSP or MPU is combined with efficient DRAM on a single IC die. To optimize the embedded memory, the chip includes wide-band connections to DRAM. Row and column addresses of DRAM can be applied at the same time using wide address busses. Additional metal lines lower the resistance of the word line in the DRAM circuits. For certain process steps, the processor block is masked off and the process steps unique to the fabrication of memory are performed on the memory block, and vice-versa. Process steps which are common to the processor and memory blocks can be performed simultaneously on the processor and memory blocks without masking off either block. Certain process steps can be employed in the fabrication of the one of the two processor and memory blocks in addition to or in lieu of processes normally used in the fabrication of that block. An electronic component (e.g., integrated circuit) incorporating the technique is suitably included in a system or subsystem having electrical functionality, such as general purpose computers, telecommunications devices, and the like.

DRAM enhanced processor

A system for interactive design, synthesis and simulation of an electronic system allowing a user to design a system either by specification of a behavioral model in a high level language such as VHDL or by graphical entry. The user can view full or partial simulation and design results simultaneously, on a single display window. The synthesis process uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is generally a series of transformations operating upon various levels of design representations. At each level, the design can be simulated and reviewed in schematic diagram form. The simulation results can be displayed immediately adjacent to signal lines on the diagram to which they correspond. In one embodiment, design rule violations are processed by an expert system to suggest possible corrections or alterations to the design which will eliminate the design rule violations. Schematic diagram and simulation displays showing those portions of the electronic system and simulated signal patterns which are related to the design rule violations are used to help the user identify and appropriately correct problems in the design.

METHOD AND SYSTEM FOR CREATING, DERIVING AND VALIDATING STRUCTURAL DESCRIPTION OF ELECTRONIC SYSTEM FROM HIGHER LEVEL, BEHAVIOR-ORIENTED DESCRIPTION, INCLUDING INTERACTIVE SCHEMATIC DESIGN AND SIMULATION

Automated photolithography of integrated circuit wafers is enabled with a processor connected to a Rayleigh derator, a form factor generator, a logic synthesizer, a layout generator, a lithography module and a wafer process. The Rayleigh derator receives manufacturing information resulting from yield data in the wafer process, and this manufacturing data is then used to derate the theoretical minimum feature size available for etching wafer masks given a known light source and object lens numerical aperture. This minimum feature size is then used by a form factor generator in sizing transistors in a net list to their smallest manufacturable size. A logic synthesizer then converts the net list into a physical design using a layout generator combined with user defined constraints. This physical design is then used by the mask lithography module to generate wafer masks for use in the semiconductor manufacturing. Manufacturing data including process and. yield parameters is then transferred back to the Rayleigh processor for use in the designing of subsequent circuits. In this way, a direct coupling exists between the measurement of wafer process parameters and the automated sizing of semiconductor devices, enabling the production of circuits having the smallest manufacturable device sizes available for the given lithography and wafer process.

Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60&deg;. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a &ldquo;tri-ister&rdquo; is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.

Hexagonal architecture

One or more antennas are formed on an integrated circuit (IC) chip and connected to other circuitry on the IC chip. Antenna configurations include loop, multi-turn loop, square spiral, long wire, or dipole. The antenna may be formed to have two or more segments which can selectively be connected to one another to alter an effective length of the antenna. Two antennas may be formed in two different metallization layers separated by an insulating layer. Additionally, an antenna may be incorporated in a heat sink structure that is joined to the IC chip. IC chips having antennas are suitably included in a system or subsystem having electrical functionality, such as general purpose computers, telecommunications devices, and the like.

On-chip antenna, and systems utilizing same

An interface device is provided which enables communications between devices having disparate protocols (e.g., USB and Ethernet), and can be fabricated on a single integrated circuit (IC) chip. A system incorporating the interface device provides plug-and-play capability for both MAC and nonMAC environments. A &ldquo;smart&rdquo; cable incorporating the interface device has the ability to recognize what type of external device using what type of protocol is connected to the &ldquo;other&rdquo; end of the cable, thereby enabling a host to communicate with the external device. An electronic component (e.g., integrated circuit) incorporating the technique is suitably included in a system or subsystem having electrical functionality, such as general purpose computers, telecommunications devices, and the like.

Configurable universal serial bus (USB) controller implemented on a single integrated circuit (IC) chip with media access control (MAC)

Programmable triangular shaped device having variable gain

Method and apparatus for significantly improving the reliability of multilevel (MLT) memory architecture. Before writing to MLT architecture, each MLT word is encoded into a coded bit stream in such a way that the resultant coded data contains the original word plus additional digits which are a function of the content of memory. During the reading of the memory, the stored data is decoded, and takes advantage of redundancy to correct and eliminate errors introduced during read and write operations of the MLT architecture. The invention is useful for systems such as general-purpose computers (PCs, workstations, etc.), telecommunications devices (telephones&mdash;wired and wireless, switches, hubs, routers, etc.), audio and visual devices (recording and playback, editing, format switching, compression, etc.), vehicles (automobiles, aircraft, trains, boats, satellites, spacecraft, etc.). Systems and subsystems may be incorporated on a single integrated circuit (IC) die having MLT RAM or enhanced MLT memory. An electronic component (e.g., integrated circuit) incorporating the technique is suitably included in a system or subsystem having electrical functionality, such as general purpose computers, telecommunications devices, and the like.

Method and apparatus for significantly improving the reliability of multilevel memory architecture

Growing community of inventors

Boulder Creek, CA, United States of America

Michael D Rostoker