Advanced Micro Devices Corporation

Cadence Design Systems, Inc.

Michael D Pedneau

Dan S Mudgett

Lars Lundgren

Hans L Magnusson

Pradeep Goyal

Victor Markus Purri

Disclosed are methods, systems, and articles of manufacture for implementing deadlock detection with formal verification techniques in an electronic design. These techniques identify one or more inputs that include at least an initial state of an electronic design and identify at least one deadlock candidate by sweeping at least a portion of a state space of the electronic design with formal verification techniques. These techniques then determine whether the at least one deadlock candidate is a real deadlock by using a second formal search with the formal verification techniques.

Methods, systems, and computer program product for implementing deadlock detection with formal verification techniques in an electronic design

A method and apparatus for improving the efficiency of the cacheability (and other attribute) determination by making the information from the region register available during linear to physical address translation, rather than serially upon completion of the address translation. Address range comparisons are made when the TLB is loaded. That is, attribute information stored in a region register or registers is compared with physical addresses corresponding to translations loaded in a translation lookaside buffer reload operation. The present invention thus advantageously removes the region register compare operation from the path to memory.

Mechanism for storing system level attributes in a translation lookaside buffer

A computer system is provided that includes a microprocessor core having an ICE interrupt line to support an in-circuit emulation mode of the computer system. An interrupt control unit coupled to the ICE interrupt line of the microprocessor core, controls a memory control unit in accordance with assertions of an external 'debug' interrupt signal and an external SMM (system management mode) interrupt signal. During normal operation, the microprocessor core executes code out of a 'normal' memory region of a system memory coupled to the memory control unit. If the debug interrupt signal is asserted while the microprocessor core is operating in normal mode, the interrupt control unit responsively asserts the ICE interrupt signal to the microprocessor core, causing the microprocessor core to read an ICE vector from the system memory and to thereafter execute ICE code. If the SMM interrupt signal is asserted while the microprocessor core is operating in normal mode, the interrupt control unit again causes assertion of the ICE interrupt signal. The microprocessor core responsively requests the ICE vector and, the interrupt control unit causes the memory control unit to translate the requested address to a second memory location of the system memory at which an SMM vector is stored. The computer system allows an in-circuit emulation mode to be entered while the microprocessor core is executing out of the system management space by asserting the debug interrupt signal.

Computer system including in-circuit emulation mode for debugging system

A processing unit is provided that generates an address signal which specifies data on a per-byte basis and that further generates a set of byte enable signals which specify enabled bytes relative to the addressed byte. Both the byte enable signals and the address signal are provided to a memory control unit. The processing unit can thereby generate a single memory access to a misaligned memory address, while still specifying a variable number of enabled bytes. A control input provided to the processing unit controls whether a bus control unit of the processing unit generates single cycle memory accesses to misaligned addresses or two-cycle memory accesses to misaligned addresses. For memory accesses to static RAM, the memory control unit may deassert the control signal such that the processing unit generates two-cycle accesses on misaligned addresses. On the other hand, for memory accesses to dynamic RAM, the memory control unit may assert the control signal such that the processing unit generates single cycle accesses on misaligned addresses, unless a page boundary is encountered. The processing unit advantageously allows single cycle accesses to misaligned addresses to thereby accommodate increased system performance, and further supports broad compatibility with existing memory systems.

Processimg unit with programmable mis-aligned byte addressing

A configuration register enables built-in testing logic during testing operations, and disables the testing logic during non-testing operations. When enabled, the testing logic is in a normal state, and when disabled the testing logic is in a low power state. The configuration register generates a control signal to the testing logic, the control signal being is responsive to signals received at a key input and a reset input of the configuration register. When the reset input of the configuration register is triggered, the control signal drives the testing logic to the low power state. When a signal matching a predetermined data pattern is applied to the key input, the control signal drives the testing logic to the normal state.

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Austin, TX, United States of America

Michael D Pedneau