Dell USA L P

Michael D Ohlinger

Deepak N Swamy

Joseph Daniel Mallory

N Deepak Swamy

H Scott Estes

Robert B Petty

An optimal routing methodology for routing high I/O density packages which minimizes the number of PCB layers required. One feature of this routing methodology comprises treating respective I/O that are routed at the top layer of the package as surface mount technology (SMT) pads without dropping vias within the BGA grid, as is commonplace in the industry. This facilitates the use of fewer escapes and allows for more efficient use of the available space. Signal lines on the top layer of the package which must be routed to other layers of the PCB are connected to vias outside of the area of local high signal density on the printed circuit board. The placement of vias outside the area of local high density, i.e., in a depopulated area, reduces the number of layers necessary in the PCB to properly route the signals. This placement also facilitates the use of filtering capacitors to meet EMI requirements. In addition, all voltage pins are placed on the innermost or outermost grids and have clearanced vias. The device is also preferably placed at the beginning or at the end of the bus to maximize the routing efficiency.

Optimal PCB routing methodology for high I/O density interconnect devices

To facilitate a grounding connection between a circuit board and a chassis upon which it is to be mounted, a spaced series of unlined mounting holes are formed through the substrate portion of the circuit board between its top and bottom sides, and spaced series of grounding vias are formed through the substrate and positioned in a circular arrays around each of the mounting holes. Annular layers of a metallic plating material are formed on the opposite sides of the circuit board substrate, around the top and bottom ends of the unlined mounting holes, with the plating material being extended along the interior side surfaces of the vias between associated top and bottom annular plating material layers. Using solder masks placed on the opposite sides of the circuit board substrate, circular arrays of solder pads are formed on the outer side surfaces of the annular plating layers, with each solder pad array being interdigitated with the vias in one of the circular arrays thereof, and being horizontally offset from the vias. The bottom side of the circuit board is secured against a side of the chassis by extending metal mounting screws through the unlined mounting holes of the circuit board and threading the screws into corresponding holes in the chassis to press the bottom side solder pads of the circuit board against the chassis.

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Austin, TX, United States of America

Michael D Ohlinger