Northrop Grumman Systems Corporation

Michael D Lange

Jesse B Tice

Vincent Gambin

Roger S Tsai

Po-Hsin Liu

Wayne Yoshida

Xiaobing Mei

Loan T Le

Peter S Nam

Ling-Shine Lee

A method for wafer-level deposition of a semiconductor layer structure including at least one two-dimensional black phosphorus layer. The method includes providing a wafer substrate and a metal catalyst layer on the substrate. The method includes heating a phosphorus material to generate a Pflux and heating the Pflux to generate a Pflux, where the Pflux is deposited on the metal catalyst layer using molecular beam epitaxy or chemical vapor deposition. The process of depositing the black phosphorus layer can include adding a dopant or alloy to the Pflux to modify the band gap of the phosphorus layer. The method includes heating the substrate to a temperature above a temperature that causes red phosphorus to evaporate from the substrate, but does not cause black phosphorus to evaporate from the substrate.

Wafer-scale catalytic deposition of black phosphorus

A method for fabricating a double-recess gate structure for an FET device that includes providing a semiconductor wafer having a plurality of semiconductor layers and depositing an EBL resist layer on the wafer. The method also includes patterning the EBL resist layer to form an opening in the EBL resist layer and performing a first wet etch to form a first recess in the wafer. The method further includes depositing a dielectric layer over the EBL resist layer and into the first recess and performing a dry etch to remove a portion of the dielectric layer in the first recess. The method also includes performing a second wet etch through the opening in the dielectric layer to form a second recess, and depositing a gate metal layer in the first and second recesses and in the opening in the EBL resist layer to form a gate terminal.

Self-aligned double gate recess for semiconductor field effect transistors

Antimony-based semiconductor devices are formed over a substrate structure () that includes an antimony-based buffer layer () and an antimony-based buffer cap (). Multiple epitaxial layers () formed over the substrate structure () are dry etched to form device mesas () and the buffer cap () provides a desirably smooth mesa floor and electrical isolation around the mesas.

Method for etching mesa isolation in antimony-based compound semiconductor structures

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Anaheim, CA, United States of America

Michael D Lange