USA As Represented by Secretary of the Navy

Michael D Haddon

Gabriel Henry Soto

Paul E Anderson

Jonathan Duncan

Calvin Clayson

Deric Keith Mason

Jerry Shultz

An electronic thermally-initiated venting system (ETIVS) for rocket motors includes at least one linear-shaped charge attached to a rocket motor housing. At least one exploding foil initiator (EFI) is attached to the linear-shaped charge. At least one electronic thermally-initiated venting system circuit is electrically-connected to the EFI. The EFI is configured to auto-fire when the electronic thermally-initiated venting system circuit relays a current pulse through the EFI. The linear-shaped charge is configured to initiate when the current pulse is relayed through the EFI.

Electronic thermally-initiated venting system (ETIVS) for rocket motors

A memory check ASIC for fuzes and safety and arming (S&A) devices. The memory check ASIC may comprise: an ASIC, data line, clock line, shutdown line, and reset line. The ASIC may operatively couple to a microcontroller having a flash-based memory and may comprise: a digital logic for verifying a calculated checksum based on contents of the flash-based memory. A clock signal along with the calculated checksum may be transmitted to the ASIC via the clock line and data line, respectively. A shutdown signal may be transmitted from the ASIC to the microcontroller via the shutdown line in response to the verification of the calculated checksum by the digital logic. A reset signal may synchronize sampling of the calculated checksum and may be latched by flip-flop circuits of the digital logic for a predetermined number of clock cycles.

Memory check ASIC for fuzes and safety and arming devices

Embodiments are directed to unpowered railgun field validation for safe-arm fuzing. Embodiments use a wire coil having an induced electromotive force voltage. At least one positive duration circuit measures the positive portion of the induced voltage. At least one positive peak duration circuit measures the peak value of the positive portion of the induced voltage. At least one negative duration circuit measures the duration value of the negative portion of the induced voltage. At least one negative peak detector circuit measures the peak value of the negative portion of the induced voltage.

Unpowered railgun field validation for safe-arm fuzing

Embodiments relate to fuze setback validation. An electronic setback validator for a launched munition safe-arm fuze includes a transient voltage suppressor. A piezoceramic element is electrically-connected to the transient voltage suppressor. A first electronic circuit is electrically-connected to the piezoceramic element and is a constant 1 milliamp discharge circuit. The first electronic circuit is configured to determine setback magnitude of acceleration. A second electronic circuit is electrically-connected to the piezoceramic element. The second electronic circuit is a constant 122 microamp charge circuit and is configured to determine setback duration of acceleration. A microcontroller is electrically-connected to the first and second electronic circuits.

Electronic setback validation for fuzes

Timing circuits including supervisor chip(s), capacitors, and latches. The supervisor chip(s) and capacitors cooperate to generate an electrical signal (window signal) having a high logic state when the window is open. The latches are used to determine whether an event of interest occurred while the window was open using the generated window signal and an electrical signal asserted upon occurrence of the event of interest.

Devices and methods using supervisor chips (integrated circuits) to generate time acceptance windows

An underwater grenade and a method for using an underwater grenade. A depth activated, hand emplaced ordnance utilizing safe and arm technology to address underwater threats (such as enemy swimmers) while providing a safe interface with personnel. The grenade is armed after a sequence of events have occurred including reaching a desired depth and a desired passage of time. Failure of any of the events to occur will cause the grenade to be rendered safe.

Underwater grenade

Electronics for a shock-hardened device, in particular a data recorder, incorporating non-volatile memory. The device has the functional elements: a signal conditioning circuit, an oscillator, an analog-to-digital converter (ADC), a field programmable gate array (FPGA), a trigger, and a non-volatile memory incorporating both electrically erasable programmable read only memory (EEPROM) and fast static random access memory (SRAM). As a recorder, the electronics enable efficient and reliable data recording in extreme shock environments, e.g., those involving dynamic testing of weapons such as target penetrating bombs or dual-stage warheads. It also provides for data retention upon loss or shutdown of power to the unit and yields high MTBF (mean time between failure) figures in more benign environments.

Electronics for a shock hardened data recorder

Electronics for a shock-hardened device, in particular a data recorder, incorporating non-volatile memory. The device has the functional elements: a signal conditioning circuit, an oscillator, an analog-to-digital converter (ADC), a field programmable gate array (FPGA), a trigger, and a non-volatile memory incorporating both electrically erasable programmable read only memory (EEPROM) and fast static random access memory (SRAM). As a recorder, the electronics enable efficient and reliable data recording in extreme shock environments, e.g., those involving dynamic testing of weapons such as target penetrating bombs or dual-stage warheads. It also provides for data retention upon loss or shutdown of power to the unit and yields high mean time between failures (MTBF) figures in more benign environments.

Disclosed, in a preferred embodiment, is a switching circuit incorporating a Field Effect Transistor (FET), two series dual-tap gas tube surge arrestors, and high-voltage resistors as part of a high voltage switch of a fireset for initiating an exploding foil initiator (EFI). Until energizing the FET via a firing command, an operating voltage of 1000 V is held off by a combination of the surge arrestors and high-voltage resistors. Upon receipt of a firing signal, a 28 V source is used to energize the FET that, in turn, decreases the voltage across the one surge arrestor connected directly to ground and increases the voltage across the other surge arrestor. Upon reaching the breakdown voltage of the ionizable gas within the second surge arrestor, the gas ionizes, becomes electrically conductive, and dumps the second surge arrestor's voltage across the first surge arrestor. This causes the first surge arrestor to also break down. Both surge arrestors are now conducting. Thus, the 1000 V source is free to energize the remainder of the circuit, discharging a 0.20 &mgr;f capacitor through the EFI. The breakdown of both arrestors occurs in nanoseconds, enabling an almost instantaneous initiation signal.

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Ridgecrest, CA, United States of America

Michael D Haddon