Advanced Micro Devices Corporation

Michael D Goddard

Scott A White

David S Christie

David B Witt

Kelvin Domnic Goveas

William M Johnson

Norman Bujanos

Nathan L Yao

Thang M Tran

Gopi Ganapathy

Robert C Thaden

Tim Olson

In a microprocessor system, a program counter circuit generates a program counter value that represents a retrieved instruction and that includes a more significant portion, a less significant portion, and a carry signal for use in determining a next program counter value. An execute program counter circuit generates an execute program counter value from the less significant program counter value and from the carry signal. The execute program counter value represents a program counter value of an executed instruction.

Program counter update mechanism

A superscalar complex instruction set computer (&ldquo;CISC&rdquo;) processor having a reduced instruction set computer (&ldquo;RISC&rdquo;) superscalar core includes an instruction cache which identifies and marks raw x86 instruction start and end points and encodes &ldquo;pre-decode&rdquo; information, a byte queue which is a queue of aligned instruction and pre-decode information of the &ldquo;predicted executed&rdquo; state, and an instruction decoder which generates type, opcode, and operand pointer values for RISC-like operations (ROPs) based on the aligned pre-decoded x86 instructions in the byte queue and determines the number of possible x86 instruction dispatch for shifting the byte que. The instruction decoder includes in each dispatch position a logic conversion path, a memory conversion path, and a common conversion path for converting CISC instructions to ROPs. An ROP multiplexer directs x86 instructions from the byte queue to the conversion paths, a select circuit assembles ROP information from the appropriate conversion paths, and a shared circuit processes ROP information from the select circuit for shared resources. ROP type and opcode information is dispatched from the instruction decoder to the RISC core. Pointers to the A and B source operands are furnished by the instruction decoder to a register file and to a reorder buffer in the RISC core, which in turn furnish the appropriate &ldquo;predicted executed&rdquo; versions of the A and B operands to various functional units in the RISC core in coordination with the ROP type and opcode information.

Superscalar instruction decoder including an instruction queue

A reservation station with format conversion logic enables the implementation of a superscalar computer processing system which incorporates both a floating point functional unit and non-floating point functional units. By converting operand data in a floating point reservation station from external formats to an internal floating point format, a system incorporating such a floating point reservation station enables the representation of operand data in uniform external formats outside floating point arithmetic units (e.g., in a reorder buffer, on operand and result busses, and within non-floating functional units) while also enabling the use of a specialized internal representation (internal floating point format) within floating point arithmetic units. A system incorporating multiple functional units and such a floating point reservation station enables the use of superscalar techniques for exploiting parallelism between floating point and non-floating point instructions because operands and results are externally represented in uniform external formats. Specialized logic within the floating point reservation station converts operand formats.

Reservation station for a floating point processing unit

A processor which includes a fetch program counter circuit and an execute program counter circuit is disclosed. The fetch program counter circuit provides less significant program counter value bits in addition to a fetch program counter value. The execute program counter circuit generates an execute program counter value using the less significant program counter value bits. The execute program counter circuit receives a plurality of less significant program counter bit values and selects a single less significant program counter bit value thus generating execute program counter values in a multiple pipeline processor.

An instruction cache for a superscalar processor having a variable byte-length instruction format, such as the X86 format, is organized as a 16K byte 4-way set-associative cache. An instruction store array is organized as 1024 blocks of 16 predecoded instruction bytes. The instruction bytes are prefetched and predecoded to facilitate the subsequent parallel decoding and mapping of up to four instructions into a sequence of one or more internal RISC-like operations (ROPs), and the parallel dispatch of up to 4 ROPs by an instruction decoder. Predecode bits are assigned to each instruction byte and are stored with the corresponding instruction byte in the instruction store array. The predecode bits include bits for identifying the starting, ending, and opcode bytes, and for specifying the number of ROPs that an instruction maps into. An address tag array is dual-ported and contains 1024 entries, each composed of a 20-bit address tag, a single valid bit for the entire block, and 16 individual byte-valid bits, one for each of the 16 corresponding instruction bytes within the instruction store array. A successor array is dual-ported and contains 1024 entries, each composed of a 14-bit successor index, a successor valid bit which indicates that the successor index stored in the successor array should be used to access the instruction store array or that no branch is predicted taken within the instruction block, and a block branch index which indicates the byte location within the current instruction block of the last instruction byte predicted to be executed.

Pre-decoded instruction cache and method therefor particularly suitable

A processor core for supporting the concurrent execution of mixed integer and floating point operations includes integer functional units (110) utilizing 32-bit operand data and a floating point functional unit (22) utilizing up to 82-bit operand data. Eight operand busses (30, 31) connect to the functional units to furnish operand data, and five result busses (32) are connected to the functional units to return results. The width of the operand busses is 41 bits, which is sufficient to communicate either integer or floating point data. This is done using an instruction decoder (18) to apportion a floating point operation which operates on 82-bit floating point operand data into multiple suboperations each associated with a 41-bit suboperand. The operand busses and result busses have an expanded data-handling dimension from the standard integer data width of 32 bits to 41 bits for handling the floating point operands. The floating point functional unit recombines the suboperand data into 82-bits for execution of the floating point operation, and partitions the 82-bit result for output to the result busses. In addition, the excess capacity of the result busses during integer transfers is used to communicate integer flags.

Plural operand buses of intermediate widths coupling to narrower width

A superscalar complex instruction set computer ('CISC') processor (100) having a reduced instruction set computer ('RISC') superscalar core (110) includes an instruction cache (104) which identifies and marks raw x86 instruction start and end points and encodes 'pre-decode' information, a byte queue (106) which is a queue of aligned instruction and pre-decode information of the 'predicted executed' state, and an instruction decoder (108) which generates type, opcode, and operand pointer values for RISC-like operations (ROPs) based on the aligned pre-decoded x86 instructions in the byte queue. The instruction decoder includes in each dispatch position a logic-based conversion path, a memory-based conversion path, and a common conversion path for converting CISC instructions to ROPs. An ROP multiplexer (400) directs x86 instructions from the byte queue to the conversion paths. The ROP multiplexer includes scan logic (690) which rapidly scans the byte queue to generate for each dispatch position an array of bits (ISELx) that identifies the location of the opcode, and ROP information signals (ROPxNUM, ROPxDIFF, PGNXT�x!). The scan logic is segregated into groups of bit processing logic (GP(x,y)) and includes a look-ahead capability (LAG(x)) between groups.

Instruction queue scanning using opcode identification

In a processor (110) that performs multiple instructions in a single cycle, predicts outcomes of branch conditions and speculatively executes instructions based on the branch predictions, a method and apparatus for operating a data stack utilize a remap array (674) to support a stack exchange capability. The remap array is used to correlate a stack pointer (672) to data elements (700) within the stack. A lookahead stack pointer (502) and remap array (504) are updated to preserve the processor's state of operation while speculative instructions are executed.

Floating point stack and exchange instruction

A superscalar microprocessor is provided with a reorder buffer for storing the speculative state of the microprocessor and a register file for storing the real state of the microprocessor. A flags register stores the real state of flags that are updated by flag modifying instructions which are executed by the functional units of the microprocessor. To enhance the performance of the microprocessor with respect to conditional branching instructions, the reorder buffer includes a flag storage area for storing flags that are updated by flag modifying instructions. The flags are renamed to make possible the earlier execution of branch instructions which depend on flag modifying instructions. If a flag is not yet determined, then a flag tag is associated with the flag storage area in place of that flag until the actual flag value is determined. A flag operand bus and a flag tag bus are provided between the flag storage area and the branching functional unit so that the requested flag or flag tags are provided to instructions which are executed in the branching functional unit.

Superscalar microprocessor including flag operand renaming and

A superscalar complex instruction set computer ('CISC') processor having a reduced instruction set ('RISC') superscalar core includes an instruction cache which identifies and marks raw x86 instruction start and end points and encodes 'predecode' information, a byte queue (BYTEQ) which is a queue of aligned instruction and predecode information of the 'predicted executed' state, and an instruction decoder (IDECODE) which generates type, opcode, and operand pointer values for RISC-like operation based on the aligned predecoded x86 instructions in the BYTEQ and determines the number of possible x86 instruction dispatch for shifting the BYTEQ. The IDECODE includes in each dispatch position a logic conversion path, a memory conversion path, and a common conversion path for converting CISC instructions to ROPs. An ROP multiplexer directs x86 instructions from the BYTEQ to the conversion paths. A select circuit (ROPSELECTx) assembles ROP information from the appropriate conversion paths. A share circuit processes ROP information from the ROPSELECTx for shared resources. ROP type and opcode information is dispatched from the IDECODE to the RISC core. Pointers to the A and B source operands are furnished by the IDECODE to a register file and to a reorder buffer in the RISC core which in turn furnish the appropriate 'predicted executed' versions of the A and B operands to various functional units in the RISC core in coordination with the ROP type and opcode information.

Method and apparatus for decoding one or more complex instructions into

A microcode patching method and apparatus provides for fetching of microcode from an external source which, under appropriate conditions, replaces direct reading of microcode from a microcode ROM. In a decoder having a capability to concurrently dispatch up to four instructions and each dispatch pathway having two alternative decoding pathways including a fastpath pathway and a microcode ROM pathway, a technique and apparatus for patching the microcode ROM is described. This technique and apparatus provides that execution codes from the microcode ROM are selectively replaced, during decoding, by codes taken from an external source, such as from an external memory via a byte queue.

Microcode patching apparatus and method

Operations of a pipeline processor (110) are resynchronized under designated conditions. The processor updates a fetch program counter (210) and, as directed by the counter, fetches instructions from a memory (114). The processor concurrently dispatches, in the fetched order, multiple instructions to designated functional units (170, 171, 172, 173, 174 and 175). Dispatched instructions are queued in functional unit reservation stations. Result entries corresponding to the queued instructions are allocated in a reorder buffer 126 queue in their order of dispatch. Instructions are executed out of their fetched order and results are entered in the allocated result entries when execution is complete. Allocated result entries at the head of the reorder buffer queue are retired and an instruction pointer (620) is updated. The processor is resynchronized when it detects a resynchronization condition and acknowledges the resynchronization condition in the allocated result entry corresponding to the instruction that detected the condition. When the reorder buffer entry holding the resynchronization acknowledgement is retired, the processor flushes the reorder buffer and the reservation stations of the functional units and redirects the fetch program counter to the instruction addressed by the instruction pointer.

Resynchronization of a superscalar processor

A reservation station with an addressable constant store enables the provision of floating point constants to arithmetic units in a floating point unit of a superscalar processor. Floating point constant identifiers supplied with floating point instructions index into the addressable store and addressed constant are provided in an internal, extended-precision format which provides extra precision and/or range when compared with formats available external to the floating point unit. In this way, full internal, extended-precision constants can be provided for use in microcoded floating point instruction sequences. Additionally, internal extended-precision floating point constants may be rounded in accordance with a prevailing rounding mode and format to provide external format floating point constant values for use in implementing load constant instructions.

Growing community of inventors

Austin, TX, United States of America

Michael D Goddard